intr_old.c

SMDK2416_BSP

        // Depending on IRQ number use internal or external mask register
        
        if (irq == IRQ_CFCON) {
            // Use interrupt mask register
            g_pATAPIRegs->ATA_IRQ = 0xff;
       	    g_pATAPIRegs->ATA_IRQ_MASK = 0xffffffe0;           
            mask = 1 << irq;
            OUTREG32(&g_pIntrRegs->SRCPND, mask);
            CLRREG32(&g_pIntrRegs->INTMSK, mask);
        } else if (irq <= IRQ_ADC) {
            // Use interrupt mask register
            mask = 1 << irq;
            OUTREG32(&g_pIntrRegs->SRCPND, mask);
            CLRREG32(&g_pIntrRegs->INTMSK, mask);
        } else if (irq <= IRQ_EINT23) {
            // Use external mask register
            mask = 1 << (irq - IRQ_EINT4 + 4);
            OUTREG32(&g_pPortRegs->EINTPEND, mask);
            CLRREG32(&g_pPortRegs->EINTMASK, mask);
        }
        else if( irq <= IRQ_AUDIO)
        {
       	} 
        else if (irq <= IRQ_DMA5)	// irq >= IRQ_DMA0 && irq <= IRQ_DMA5
        {
        	//RETAILMSG(1,(TEXT("DMA!! Interrupt Done!! -- %d\n"),irq));
         	mask = 1 << (IRQ_SUB_DMA5 - (IRQ_DMA5 - irq));	
         	OUTREG32(&g_pIntrRegs->SUBSRCPND, mask);
         	CLRREG32(&g_pIntrRegs->INTSUBMSK, mask);
     	}   
     	else if(irq == IRQ_LCD_VSYNC)
     	{
  			OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_LCD3) );			// Clear LCD3 sub source pending register bit
  			CLRREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_LCD3) );		// masking LCD3 sub interrupt			
     	}  
    }

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-OALIntrDoneIrqs\r\n"));
}


//------------------------------------------------------------------------------
//
//  Function:  OEMInterruptHandler
//
ULONG OEMInterruptHandler(ULONG ra)
{
    UINT32 sysIntr = SYSINTR_NOP;
    UINT32 irq, irq2, mask;
    static DWORD HeartBeatCnt, HeartBeatStat;  //LED4 is used for heart beat
    static DWORD DMA2CNT=0;
    
    // Get pending interrupt(s)
    irq = INREG32(&g_pIntrRegs->INTOFFSET);

    // System timer interrupt?
    if (irq == IRQ_TIMER4) {

	if (++HeartBeatCnt > 100)
	{
		HeartBeatCnt   = 0;
		HeartBeatStat ^= 1;
		g_pPortRegs->GPFCON = (g_pPortRegs->GPFCON & ~(3<<8)) | (1<<8); // GPF4 Output
		if (HeartBeatStat) 
		{
			g_pPortRegs->GPFDAT &= ~(1<<4); // LED 4 Off
		}
		else
		{
			g_pPortRegs->GPFDAT |=  (1<<4); // LED 4 On
		}
	}

        // Rest is on timer interrupt handler
        sysIntr = OALTimerIntrHandler();
	}    
    // Profiling timer interrupt?
    else if (irq == IRQ_TIMER2)
    {
        // Mask and Clear the interrupt.
        mask = 1 << irq;
        SETREG32(&g_pIntrRegs->INTMSK, mask);
        OUTREG32(&g_pIntrRegs->SRCPND, mask);
        OUTREG32(&g_pIntrRegs->INTPND, mask);
        INREG32(&g_pIntrRegs->INTPND);

        // The rest is up to the profiling interrupt handler (if profiling
        // is enabled).
        //
        if (g_pProfilerISR)
        {
            sysIntr = g_pProfilerISR(ra);
        }
    }
    else 
    {

#ifdef OAL_ILTIMING
        if (g_oalILT.active) {
            g_oalILT.isrTime1 = OALTimerCountsSinceSysTick();
            g_oalILT.savedPC = 0;
            g_oalILT.interrupts++;
        }        
#endif
    
        if (irq == IRQ_EINT4_7 || irq == IRQ_EINT8_23) { // 4 or 5

            // Find external interrupt number
            mask = INREG32(&g_pPortRegs->EINTPEND);
            mask &= ~INREG32(&g_pPortRegs->EINTMASK);
            mask = (mask ^ (mask - 1)) >> 5;
            irq2 = IRQ_EINT4;
            while (mask != 0) {
                mask >>= 1;
                irq2++;
            }

            // Mask and clear interrupt
            mask = 1 << (irq2 - IRQ_EINT4 + 4);
            SETREG32(&g_pPortRegs->EINTMASK, mask);
            OUTREG32(&g_pPortRegs->EINTPEND, mask);

            // Clear primary interrupt
            mask = 1 << irq;
            OUTREG32(&g_pIntrRegs->SRCPND, mask);
            OUTREG32(&g_pIntrRegs->INTPND, mask);
            INREG32(&g_pIntrRegs->INTPND);

            // From now we care about this irq
            irq = irq2;

        }  
      else if(irq == IRQ_CAM)
        {
        	if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_CAM_C))
        	{
	        	  SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_CAM_C));
	        	  SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_CAM));
	        	  OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_CAM_C));
	        	  OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_CAM));
	        	  OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_CAM));
	        	  INREG32(&g_pIntrRegs->INTPND);
	        	  //RETAILMSG(1,(TEXT("IRQ_CAM Codec\r\n")));
        	}
        	
        	else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_CAM_P))
         	{
	        	  SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_CAM_P));
	        	  SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_CAM));
	        	  OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_CAM_P));
	        	  OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_CAM));
	        	  OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_CAM));
	        	  INREG32(&g_pIntrRegs->INTPND);
	        	  //RETAILMSG(1,(TEXT("PreView\r\n")));
        	}
        	
        	else
        	{
        		SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_CAM_C)|(1<<IRQ_SUB_CAM_P)); 
        		SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_CAM));
        		SETREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_CAM_C)|(1<<IRQ_SUB_CAM_P));       	  
        		OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_CAM));
        		OUTREG32(&g_pIntrRegs->INTPND,(1<<IRQ_CAM));
        		INREG32(&g_pIntrRegs->INTPND);
        	       // RETAILMSG(1,(TEXT("nop\r\n")));        		
        		return SYSINTR_NOP; 
        	}
        }
		else if(irq == IRQ_LCD)
		{    
			sysIntr = SYSINTR_NOP;
      		if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1 << IRQ_SUB_LCD3) )				 
      		{
      			if ( (INREG32(&g_pLCDRegs->VIDCON1) & LCD_VSTATUS) )
      			{      		
      				SETREG32(&g_pIntrRegs->INTSUBMSK, (1 << IRQ_SUB_LCD3) );		// masking LCD3 sub interrupt		
      				//RETAILMSG(1,(TEXT("+")));
      				irq = IRQ_LCD_VSYNC;
      			}
      			OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_LCD3) );			// Clear LCD3 sub source pending register bit
      		}
			OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_LCD) );							// Clear LCD source pending register bit
			OUTREG32(&g_pIntrRegs->INTPND, (1<<IRQ_LCD) );							// Clear LCD interrupt register bit
			INREG32(&g_pIntrRegs->INTPND);											// confirm
		}  
        else if(irq == IRQ_DMA)
        {
        	SETREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_DMA));
        	//RETAILMSG(1,(TEXT("DMA\n")));
        	if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA0))
        	{
        	  	SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA0));
        	  	OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA0));
        	  	irq = IRQ_DMA0;
        	}
        	else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA1))
        	{
        		//RETAILMSG(1,(TEXT("DMA1\n")));
        		//RETAILMSG(1,(TEXT("g_pIntrRegs->SUBSRCPND=0x%08X\n"),g_pIntrRegs->SUBSRCPND));
        		SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA1));
        		OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA1));
        		
        		irq = IRQ_DMA1;
        	} 
        	else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA2))
        	{

       			//RETAILMSG(1,(TEXT("DMA2\n")));
   
        		SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA2));
        		OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA2));
        		irq = IRQ_DMA2;
        	} 
        	else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA3))
        	{
	        	SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA3));
	        	OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA3));
        	    irq = IRQ_DMA3;
        	} 
        	else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA4))
        	{
				SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA4));
				OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA4));
				irq = IRQ_DMA4;
        	}   
        	else if(INREG32(&g_pIntrRegs->SUBSRCPND) & (1<<IRQ_SUB_DMA5))
        	{
				SETREG32(&g_pIntrRegs->INTSUBMSK, (1<<IRQ_SUB_DMA5));
				OUTREG32(&g_pIntrRegs->SUBSRCPND, (1<<IRQ_SUB_DMA5));
				irq = IRQ_DMA5;
        	}         	      	        	        	       	
        	OUTREG32(&g_pIntrRegs->SRCPND, (1<<IRQ_DMA));
        	OUTREG32(&g_pIntrRegs->INTPND, (1<<IRQ_DMA));
        	INREG32(&g_pIntrRegs->INTPND);
        	CLRREG32(&g_pIntrRegs->INTMSK, (1<<IRQ_DMA));
        }      	

        else if(irq == IRQ_CFCON)
        {
       	    if ( !(g_pATAPIRegs->ATA_IRQ & 0x1))
       	    {
       	    	g_pATAPIRegs->ATA_IRQ = 0xff;
            	OUTREG32(&g_pIntrRegs->SRCPND, 1<<IRQ_CFCON );
            	OUTREG32(&g_pIntrRegs->INTPND, 1<<IRQ_CFCON );   
            	INREG32(&g_pIntrRegs->INTPND);    	    	
        	return SYSINTR_NOP;       	    	
       	    }

       	    g_pATAPIRegs->ATA_IRQ_MASK = 0xffffffff;
       	    g_pATAPIRegs->ATA_IRQ = 0xff;       	    
            SETREG32(&g_pIntrRegs->INTMSK, 1<<IRQ_CFCON );
            OUTREG32(&g_pIntrRegs->SRCPND, 1<<IRQ_CFCON );
            OUTREG32(&g_pIntrRegs->INTPND, 1<<IRQ_CFCON );  
            INREG32(&g_pIntrRegs->INTPND);      		
       	}
        	
        	
	else {
            // Mask and clear interrupt
            mask = 1 << irq;
            SETREG32(&g_pIntrRegs->INTMSK, mask);
            OUTREG32(&g_pIntrRegs->SRCPND, mask);
            OUTREG32(&g_pIntrRegs->INTPND, mask);
            INREG32(&g_pIntrRegs->INTPND);
        }

        // First find if IRQ is claimed by chain
        sysIntr = NKCallIntChain((UCHAR)irq);
        if (sysIntr == SYSINTR_CHAIN || !NKIsSysIntrValid(sysIntr)) {
            // IRQ wasn't claimed, use static mapping
            sysIntr = OALIntrTranslateIrq(irq);
        }
    }

	//g_oalLastSysIntr = sysIntr;
    return sysIntr;
}

//------------------------------------------------------------------------------