📄 startup.s
字号:
ldr r2, =BANKCON1
ldr r1, [r2]
bic r1, r1, #(0x3<<0)
orr r1, r1, #(0x1<<0) ; 4nd : Issue a PALL command (to BANKCON1)
str r1, [r2]
ldr r4, =REFRESH ; 5fh : Refresh cycle every 255-clock cycles (to REFRESH)
ldr r0, =0xff
str r0, [r4]
mov r0, #0x100 ; 6th : wait 2 auto - clk
120
subs r0, r0, #1
bne %B120
bic r1, r1, #(0x3<<0)
orr r1, r1, #(0x2<<0) ; 7th : Issue a MRS command (to BANKCON1)
str r1, [r2]
ldr r4, =REFRESH ; 8fh : Refresh cycle normal (to REFRESH)
ldr r0, =REFCYC
str r0, [r4]
orr r1, r1, #(0x3<<0) ; 9th : Issue a EMRS command (to BANKCON1)
str r1, [r2]
bic r1, r1, #(0x3<<0) ; 10th : Issue a Normal mode (to BANKCON1)
str r1,[r2]
mov pc, lr
]
[ BSP_TYPE = BSP_SMDK2450
IF :DEF: mSDR
InitMEM
;Set GPK port when using x32 bus width.
ldr r0,=GPKCON
ldr r1,=0xaaaaaaaa ; set Sdata[31:16]
str r1, [r0]
;Set SDR Memory parameter control registers
ldr r0,=BANKCFG
ldr r1,=BANKCFGVAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON1
ldr r1,=BANKCON1VAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON2
ldr r1,=BANKCON2VAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON3
ldr r1,=BANKCON3VAL ; set Sdata[31:16]
str r1, [r0]
; ldr r2,=RSTSTAT ;
; ldr r1,[r2]
; cmp r1, #0x1
; bne GOM
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x1<<0) ; 4nd : Issue a PALL command
str r1,[r2]
ldr r4,=REFRESH ; 5fh : refresh cycle every 255-clock cycles
ldr r0,=0xff
str r0,[r4]
mov r0, #0x100 ; 6th : wait 2 auto - clk
2 subs r0, r0,#1;
bne %B02
bic r1,r1,#(0x3<<0) ; 7th : Issue a MRS command
orr r1,r1,#(0x2<<0)
str r1,[r2]
ldr r4,=REFRESH ; 8fh : refresh normal
ldr r0,=REFCYC
str r0,[r4]
orr r1,r1,#(0x3<<0) ; 9th : Issue a EMRS command
str r1,[r2]
bic r1,r1,#(0x3<<0) ; 10th : Issue a Normal mode
str r1,[r2]
mov pc, lr
ENDIF
IF :DEF: mDDR
InitMEM
;Set GPK port when using x32 bus width.
ldr r0,=GPKCON
ldr r1,=0xaaaaaaaa ; set Sdata[31:16]
str r1, [r0]
;Set DDR Memory parameter control registers
ldr r0,=BANKCFG
ldr r1,=BANKCFGVAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON1
ldr r1,=BANKCON1VAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON2
ldr r1,=BANKCON2VAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON3
ldr r1,=BANKCON3VAL ; set Sdata[31:16]
str r1, [r0]
; ldr r2,=RSTSTAT ;
; ldr r1,[r2]
; cmp r1, #0x1
; bne GOM
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x1<<0) ; 4nd : Issue a PALL command
str r1,[r2]
ldr r4,=REFRESH ; 5fh : refresh cycle every 255-clock cycles
ldr r0,=0xff
str r0,[r4]
mov r0, #0x100 ; 6th : wait 2 auto - clk
2 subs r0, r0,#1;
bne %B02
bic r1,r1,#(0x3<<0) ; 7th : Issue a MRS command
orr r1,r1,#(0x2<<0)
str r1,[r2]
ldr r4,=REFRESH ; 8fh : refresh normal
ldr r0,=REFCYC
str r0,[r4]
orr r1,r1,#(0x3<<0) ; 9th : Issue a EMRS command
str r1,[r2]
bic r1,r1,#(0x3<<0) ; 10th : Issue a Normal mode
str r1,[r2]
mov pc, lr
ENDIF
IF :DEF: DDR2
InitMEM
;Set GPK port when using x32 bus width.
ldr r0,=GPKCON
ldr r1,=0xaaaaaaaa ; set Sdata[31:16]
str r1, [r0]
;Set DDR2 Memory parameter control registers
ldr r0,=BANKCFG
ldr r1,=BANKCFGVAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON1
ldr r1,=BANKCON1VAL ; set Sdata[31:16]
str r1, [r0]
ldr r0,=BANKCON2
ldr r1,=BANKCON2VAL ; set Sdata[31:16]
str r1, [r0]
; ldr r2,=RSTSTAT ;
; ldr r1,[r2]
; cmp r1, #0x1
; bne GOM
ldr r2,=BANKCON1 ; 4nd : Issue a PALL command
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x1<<0)
str r1,[r2]
ldr r2,=BANKCON3 ; 5th : Issue a EMRS2 command
ldr r3,=0xffff0000
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,#(BA_EMRS2<<30)
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x3<<0)
str r1,[r2]
ldr r2,=BANKCON3 ; 6th : Issue a EMRS3 command
ldr r3,=0xffff0000
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,#(BA_EMRS3<<30)
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x3<<0)
str r1,[r2]
ldr r2,=BANKCON3 ; 7th : Issue a EMRS1 command
ldr r3,=0xffff0000
ldr r4,=((BA_EMRS1<<30)+(RDQS_DIS<<27)+(nDQS_DIS<<26)+(OCD_MODE_EXIT<<23)+(DLL_EN<<16))
; (0x1<<30)|(0x0<<27)|(0x1<<26)|(0x0<<23)|(0x0<<16)
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,r4
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x3<<0)
str r1,[r2]
ldr r2,=BANKCON3 ; 8th : Issue a MRS command
ldr r3,=0xffff
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,#((BA_MRS<<14)+(DLL_RESET_HIGH<<8)+(TM<<7)+(CL_MRS<<4))
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x2<<0)
str r1,[r2]
ldr r2,=BANKCON1 ; 9nd : Issue a PALL command
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x1<<0)
str r1,[r2]
ldr r4,=REFRESH ; 10th : wait 2 auto - clk
ldr r0,=0x20
str r0,[r4]
ldr r2,=BANKCON3 ; 11th : Issue a MRS command
ldr r3,=0xffff
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,#((BA_MRS<<14)+(DLL_RESET_LOW<<8)+(TM<<7)+(CL_MRS<<4))
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x2<<0)
str r1,[r2]
mov r0, #0x100 ; Wait 200 clock
2 subs r0, r0,#1;
bne %B2
ldr r2,=BANKCON3 ; 12th : Issue a EMRS1 command For OCD Mode Set to default
ldr r3,=0xffff0000
ldr r4,=((BA_EMRS1<<30)+(RDQS_DIS<<27)+(nDQS_DIS<<26)+(OCD_MODE_DEFAULT<<23)+(DLL_EN<<16))
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,r4
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x3<<0)
str r1,[r2]
ldr r2,=BANKCON3
ldr r3,=0xffff0000
ldr r4,=((BA_EMRS1<<30)+(RDQS_DIS<<27)+(nDQS_DIS<<26)+(OCD_MODE_EXIT<<23)+(DLL_EN<<16))
ldr r1,[r2]
bic r1,r1,r3
orr r1,r1,r4
str r1,[r2]
ldr r2,=BANKCON1
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
orr r1,r1,#(0x3<<0)
str r1,[r2]
ldr r4,=REFRESH ; 13fh : refresh normal
ldr r0,=REFCYC
str r0,[r4]
ldr r2,=BANKCON1 ; 14th : Issue a Normal mode
ldr r1,[r2]
bic r1,r1,#(0x3<<0)
str r1,[r2]
;GOM mov pc, lr
ENDIF
]
;-----------------------------
; Static Memory Controller initialize
InitSSMC
; Set SMC Memory parameter control registers : AMD Flash
ldr r0, =SMBIDCYR0
ldr r1, =IDCY0
str r1, [r0]
ldr r0, =SMBWSTRDR0
ldr r1, =WSTRD0
str r1, [r0]
ldr r0, =SMBWSTWRR0
ldr r1, =WSTWR0
str r1, [r0]
ldr r0, =SMBWSTOENR0
ldr r1, =WSTOEN0
str r1, [r0]
ldr r0, =SMBWSTWENR0
ldr r1, =WSTWEN0
str r1, [r0]
ldr r0, =SMBCR0
ldr r1, =(SMBCR0_2+SMBCR0_1+SMBCR0_0)
str r1, [r0]
ldr r0,=SMBWSTBRDR0
ldr r1,=WSTBRD0
str r1,[r0]
ldr r0, =SMBWSTBRDR0
ldr r1, =WSTBRD0
str r1, [r0]
ldr r0, =SSMCCR
ldr r1, =((MemClkRatio<<1)+(SMClockEn<<0))
str r1, [r0]
ldr r0, =SMBWSTRDR5
ldr r1, =0xe
str r1, [r0]
mov pc, lr
LTORG
[ BSP_TYPE = BSP_SMDK2443
MEMDATA DATA
DCD ((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<2)+(BW<<0))
DCD ((DQS<<28)+(Reserved0<<26)+(BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4)+(BANKINIT<<0))
DCD ((tRAS<<20)+(tRC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
DCD ((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))
]
[ BSP_TYPE = BSP_SMDK2450
]
;------------------------------------
; MMU Cache/TLB/etc on/off functions
R1_I EQU (1<<12)
R1_C EQU (1<<2)
R1_A EQU (1<<1)
R1_M EQU (1)
;R1_iA EQU (1<<31)
;R1_nF EQU (1<<30)
; void MMU_EnableICache(void);
LEAF_ENTRY MMU_EnableICache
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_I
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
; void MMU_SetAsyncBusMode(void);
; FCLK:HCLK= 1:2
LEAF_ENTRY MMU_SetAsyncBusMode
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
; NAND code...
;
A410_BASE_ADDR EQU 0x2000000
;;; MACRO
;;; LDR4STR1 $src,$tmp1,$tmp2
;;; ldrb $tmp1,[$src]
;;; ldrb $tmp2,[$src]
;;; orr $tmp1,$tmp1,$tmp2,LSL #8
;;; ldrb $tmp2,[$src]
;;; orr $tmp1,$tmp1,$tmp2,LSL #16
;;; ldrb $tmp2,[$src]
;;; orr $tmp1,$tmp1,$tmp2,LSL #24
;;; MEND
EXPORT __RdPage512
__RdPage512
;input:a1(r0)=pPage
stmfd sp!,{r1-r11}
ldr r1,=0x4e000010 ;NFDATA
mov r2,#0x200
10
ldr r4,[r1]
ldr r5,[r1]
ldr r6,[r1]
ldr r7,[r1]
ldr r8,[r1]
ldr r9,[r1]
ldr r10,[r1]
ldr r11,[r1]
stmia r0!,{r4-r11}
subs r2,r2,#32
bne %B10
ldmfd sp!,{r1-r11}
mov pc,lr
END
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -