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; BANKCON2 register : DRAM timing control
;---------------------------------------
tRAS EQU 4 ; Row active time
tRC EQU 7 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
;---------------------------------------
; REFRESH register : refresh register
;---------------------------------------
REFCYC EQU 514 ; refresh cycle
]
]
]
]
]
[ BSP_TYPE = BSP_SMDK2450
IF :DEF: mSDR
;---------------------------------------
; BANKCFG register : SDRAM configure
;---------------------------------------
RASBW0 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
RASBW1 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
CASBW0 EQU 1 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
CASBW1 EQU 1 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
ADDRCFG0 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
ADDRCFG1 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
MEMCFG EQU 2 ; Ext.Mem 000=SDR,010=MSDR,100=DDRz,110=MDDR,001=DDR2
BW EQU 0 ; Bus width 00=32bit,01=16bit
;---------------------------------------
; BANKCON1 register : SDRAM timing control
;---------------------------------------
BStop EQU 0 ; read burst stop control
WBUF EQU 1 ; write buffer control
;;AP EQU 1 ; auto precharge control
;;PWRDN EQU 0 ; power down mode
AP EQU 0 ; auto precharge control
PWRDN EQU 1 ; power down mode
DQSDelay EQU 4 ; DQS delay
;-----------------------[SDRAM]-------------------------------
; HCLK tRAS tARFC CAS tRCD RP REFCYC
;---------------------------------------------------------------
;18MHz 0 1 3 0 0 140
;36MHz 1 2 3 0 0 280
; 100Mhz 5 7 3 1 1 780
; 110Mhz 5 7 3 2 2 858
; 120Mhz 6 7 3 2 2 936
; 133Mhz 6 10 3 2 2 1037
; 133.5Mhz 6 10 3 2 2 1041
; 135Mhz 6 10 3 2 2 1053
; 136Mhz 6 10 3 2 2 1060
; 136.5Mhz 6 10 3 2 2 1064
; 137.3Mhz 6 10 3 2 2 1070
; 138Mhz 6 10 3 2 2 1076
; 138.67Mhz 6 10 3 2 2 1081
; 140Mhz 6 11 3 3 3 1092 (out of spec)
; 141Mhz 6 11 3 3 3 1099
; 142Mhz 7 11 3 3 3 1107 (out of spec)
; 143.6Mhz 7 11 3 3 3 1120 (out of spec)
;---------------------------------------------------------------
;---------------------------------------
; BANKCON2 register : SDRAM timing control
;---------------------------------------
[ HCLKVAL = 18
tRAS EQU 4 ; Row active time
tARFC EQU 6 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 1 ; RAS to CAS delay
tRP EQU 1 ; Row pre-charge time
]
[ HCLKVAL = 133
tRAS EQU 6 ; Row active time
tARFC EQU 10 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
]
[ HCLKVAL = 100
tRAS EQU 5 ; Row active time
tARFC EQU 7 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
]
;---------------------------------------
; BANKCON3 register : SDRAM MRS/EMRS register
;---------------------------------------
BA_EMRS EQU 2 ; BA : EMRS
DS EQU 0 ; Driver strength
PASR EQU 0 ; PASR
BA_MRS EQU 0 ; BA : MRS
TM EQU 0 ; Test Mode - mode register set
CL_MRS EQU 3 ; CAS Latency
;---------------------------------------
; REFRESH register : SDRAM refresh register
[ HCLKVAL = 18
REFCYC EQU 140 ; refresh cycle
]
[ HCLKVAL = 133
REFCYC EQU 1037 ; refresh cycle
]
[ HCLKVAL = 100
REFCYC EQU 780 ; refresh cycle
]
ENDIF
IF :DEF: mDDR
;---------------------------------------
; BANKCFG register : mDDR SDRAM configure
;---------------------------------------
RASBW0 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
RASBW1 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
CASBW0 EQU 2 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
CASBW1 EQU 2 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
ADDRCFG0 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
ADDRCFG1 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
MEMCFG EQU 6 ; Ext.Mem 000=SDR,010=MSDR,100=DDRz,110=MDDR,001=DDR2
BW EQU 1 ; Bus width 00=32bit,01=16bit
;---------------------------------------
; BANKCON1 register : mDDR SDRAM timing control
;---------------------------------------
BStop EQU 0 ; read burst stop control
WBUF EQU 1 ; write buffer control
;;AP EQU 1 ; auto precharge control
;;PWRDN EQU 1 ; power down mode
AP EQU 0 ; auto precharge control
PWRDN EQU 1 ; power down mode
DQSDelay EQU 4 ; DQS delay
;-----------------------[mDDR SDRAM]--------------------------
; HCLK tRAS tARFC CAS tRCD tRP REFCYC
;---------------------------------------------------------------
;18MHz 0 1 3 0 0 140
;36MHz 1 2 3 0 0 280
;100Mhz 4 7 3 2 2 780
;110Mhz 4 8 3 2 2 858
;120Mhz 5 9 3 2 2 936
;133Mhz 5 10 3 2 2 1037
;---------------------------------------------------------------
;---------------------------------------
; BANKCON2 register : mDDR SDRAM timing control
;---------------------------------------
[ HCLKVAL = 18
tRAS EQU 0 ; Row active time
tARFC EQU 1 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 0 ; RAS to CAS delay
tRP EQU 0 ; Row pre-charge time
]
[ HCLKVAL = 133
tRAS EQU 5 ; Row active time
tARFC EQU 10 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
]
[ HCLKVAL = 100
tRAS EQU 4 ; Row active time
tARFC EQU 7 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 2 ; RAS to CAS delay
tRP EQU 2 ; Row pre-charge time
]
;---------------------------------------
; BANKCON3 register : mDDR SDRAM MRS/EMRS register
;---------------------------------------
BA_EMRS EQU 2 ; BA : EMRS
DS EQU 0 ; Driver strength
PASR EQU 0 ; PASR
BA_MRS EQU 0 ; BA : MRS
TM EQU 0 ; Test Mode - mode register set
CL_MRS EQU 3 ; CAS Latency
;---------------------------------------
; REFRESH register : mDDR SDRAM refresh register
;--------------------------------------
[ HCLKVAL = 18
REFCYC EQU 140 ; refresh cycle
]
[ HCLKVAL = 133
REFCYC EQU 1037 ; refresh cycle
]
[ HCLKVAL = 100
REFCYC EQU 780 ; refresh cycle
]
;---------------------------------------------------------------------------
ENDIF
IF :DEF: DDR2
;---------------------------------------
; BANKCFG register : DDR2 SDRAM configure
;---------------------------------------
RASBW0 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
RASBW1 EQU 2 ; RAS addr 00=11bit,01-12bit,10=13bit, 11=14bit
CASBW0 EQU 2 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
CASBW1 EQU 2 ; CAS addr 00=8bit,01-9bit,10=10bit, 11=11bit
ADDRCFG0 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
ADDRCFG1 EQU 1 ; addre configure
; 00={BA,RAS,CAS}, 01={RAS,BA,CAS}
MEMCFG EQU 1 ; Ext.Mem 000=SDR,010=MSDR,100=DDRz,110=MDDR,001=DDR2
BW EQU 1 ; Bus width 00=32bit,01=16bit
;---------------------------------------
; BANKCON1 register : DDR2 SDRAM timing control
;---------------------------------------
PADLOAD EQU 1
BStop EQU 0 ; read burst stop control
WBUF EQU 1 ; write buffer control
AP EQU 0 ; auto precharge control
;;PWRDN EQU 0 ; power down mode
PWRDN EQU 1 ; power down mode
DQSDelay EQU 4 ; DQS delay
;-----------------------[DDR2 SDRAM]--------------------------
; HCLK tRAS tARFC CAS tRCD tRP REFCYC
;---------------------------------------------------------------
;18MHz 0 1 3 0 0 140
;36MHz 1 3 3 1 1 280
;100Mhz 4 10 3 1 1 780
;110Mhz 4 11 3 1 1 858
;120Mhz 4 12 3 1 1 936
;133Mhz 5 13 3 1 1 1037
;---------------------------------------------------------------
;---------------------------------------
; BANKCON2 register : DDR2 SDRAM timing control
;---------------------------------------
[ HCLKVAL = 18
tRAS EQU 0 ; Row active time
tARFC EQU 1 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 0 ; RAS to CAS delay
tRP EQU 0 ; Row pre-charge time
]
[ HCLKVAL = 133
tRAS EQU 5 ; Row active time
tARFC EQU 13 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 1 ; RAS to CAS delay
tRP EQU 1 ; Row pre-charge time
]
[ HCLKVAL = 100
tRAS EQU 4 ; Row active time
tARFC EQU 10 ; Row cycle time
CL EQU 3 ; CAS latency control
tRCD EQU 1 ; RAS to CAS delay
tRP EQU 1 ; Row pre-charge time
]
;---------------------------------------
; BANKCON3 register : DDR2 SDRAM MRS/EMRS register
;---------------------------------------
BA_EMRS1 EQU 1 ; BA : EMRS
DLL_DIS EQU 1
DLL_EN EQU 0
nDQS_DIS EQU 1
RDQS_DIS EQU 0
OCD_MODE_EXIT EQU 0
OCD_MODE_DEFAULT EQU 7
BA_EMRS2 EQU 2 ; BA : EMRS
BA_EMRS3 EQU 3 ; BA : EMRS
DS EQU 0 ; Driver strength
PASR EQU 0 ; PASR
BA_MRS EQU 0 ; BA : MRS
TM EQU 0 ; Test Mode - mode register set
CL_MRS EQU 3 ; CAS Latency
DLL_RESET_HIGH EQU 1
DLL_RESET_LOW EQU 0
;---------------------------------------
; REFRESH register : DDR2 SDRAM refresh register
;---------------------------------------
[ HCLKVAL = 18
REFCYC EQU 140 ; refresh cycle
]
[ HCLKVAL = 133
REFCYC EQU 1037 ; refresh cycle
]
[ HCLKVAL = 100
REFCYC EQU 780 ; refresh cycle
]
;---------------------------------------------------------------------------
ENDIF
]
[ BSP_TYPE = BSP_SMDK2450
BANKCFGVAL EQU ((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<1)+(BW<<0))
BANKCON1VAL EQU ((DQSDelay<<28)+(1<<26)+(BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4))
BANKCON2VAL EQU ((tRAS<<20)+(tARFC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
IF :DEF: mSDR
BANKCON3VAL EQU ((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))
ENDIF
IF :DEF: mDDR
BANKCON3VAL EQU ((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))
ENDIF
]
END
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