📄 s3c2450.inc
字号:
RTCCON EQU 0x57000040
RTCALM EQU 0x57000050
ALMSEC EQU 0x57000054 ;Alarm second
ALMMIN EQU 0x57000058 ;Alarm minute
ALMHOUR EQU 0x5700005c ;Alarm Hour
ALMDATE EQU 0x57000060 ;Alarm date // edited by junon
ALMMON EQU 0x57000064 ;Alarm month
ALMYEAR EQU 0x57000068 ;Alarm year
BCDSEC EQU 0x57000070 ;BCD second
BCDMIN EQU 0x57000074 ;BCD minute
BCDHOUR EQU 0x57000078 ;BCD hour
BCDDATE EQU 0x5700007c ;BCD date //edited by junon
BCDDAY EQU 0x57000080 ;BCD day //edited by junon
BCDMON EQU 0x57000084 ;BCD month
BCDYEAR EQU 0x57000088 ;BCD year
]
[ BSP_TYPE = BSP_SMDK2450
]
;---------------------------------------
; nGCS0 = AMD Flash = Bank0 Controller Parameter setting
;---------------------------------------
GBLL AMDBOOT ; bacnk0, 16-bit and flash
; GBLL NANDBOOT ; bacnk0, 8-bit nand
IF :DEF: AMDBOOT
IDCY0 EQU 0x0 ; Idle or turnaround cycles IDCY*HCLK
WSTRD0 EQU 0xe ; Read wait state = tacc
WSTWR0 EQU 0xe ; wrie wait state
WSTOEN0 EQU 0 ; output enable assertion delay from CS
WSTWEN0 EQU 0 ; write enable assertion delay
BlWriteEn EQU 1 ;bit21-SMBAA signal control:0-1at all times, 1 active for sync
AddrValidWriteEn EQU 1 ;bit20-SMADDRVALD during write:0-always high,1-active for write
BurstLenWrite EQU 0 ;bit1819-burst transfer length:0-4,1-8,3-continu(sync only)
SyncWriteDev EQU 0 ;bit17-0:async, 1:sync
BMWrite EQU 0 ;bit16-burt mode write : 0-non-burst, 1-burst
WrapRead EQU 0 ;bit14-0-disable, 1 enable
BlReadEn EQU 1 ;bit13-SMBAA signal :0-1 at all time, 1-active for sync read
AddrValidReadEn EQU 1 ;bit12-SMADDRVALID signal: 0-always HIGH, 1-active for async & sync read
BurstLenRead EQU 0 ;bit1011-burst transfer length:0-4,1-8,2-16,3-cont(sync only)
SyncReadDev EQU 0 ;bit9-sync access :0-async, 1-sync
BMRead EQU 0 ;bit8-burst mode red and async page mode
SMBLSPOL EQU 0 ;bit6-polarit of signal nSMBLS
MW EQU 1 ;bit45-memory width : 00-8bit,01-16bit,10-32bit
WP EQU 0 ;bit3-write protect
WaitEn EQU 0 ;bit2-external wait signal enable
WaitPol EQU 0 ;bit1-polarity of the external wait input for actiation
RBLE EQU 0 ;bit0-read byte lane enable
SMBCR0_0 EQU ((BMRead<<8)+(SMBLSPOL<<6)+(MW<<4)+(WP<<3)+(WaitEn<<2)+(WaitPol<<1)+RBLE)
SMBCR0_1 EQU ((WrapRead<<14)+(BlReadEn<<13)+(AddrValidReadEn<<12)+(BurstLenRead<<10)+(SyncReadDev<<9))
SMBCR0_2 EQU ((BlWriteEn<<21)+(AddrValidWriteEn<<20)+(BurstLenWrite<<18)+(SyncWriteDev<<17)+(BMWrite<<16))
WaitTourErr0 EQU 0 ; external wait timeout error flag
WSTBRD0 EQU 0x1f ; burst read wait state
MemClkRatio EQU 1 ; SMMEMCLK :0-HCLK,1-HCLK/2,2-HCLK/3
SMClockEn EQU 1 ; SMCLK enable 0-only active during mem access,1-always running
ELSE ; NAND Boot....
IDCY0 EQU 0x0 ; Idle or turnaround cycles IDCY*HCLK
WSTRD0 EQU 0xe ; Read wait state = tacc
WSTWR0 EQU 0xe ; wrie wait state
WSTOEN0 EQU 0 ; output enable assertion delay from CS
WSTWEN0 EQU 0 ; write enable assertion delay
BlWriteEn EQU 1 ;bit21-SMBAA signal control:0-1at all times, 1 active for sync
AddrValidWriteEn EQU 1 ;bit20-SMADDRVALD during write:0-always high,1-active for write
BurstLenWrite EQU 0 ;bit1819-burst transfer length:0-4,1-8,3-continu(sync only)
SyncWriteDev EQU 0 ;bit17-0:async, 1:sync
BMWrite EQU 0 ;bit16-burt mode write : 0-non-burst, 1-burst
WrapRead EQU 0 ;bit14-0-disable, 1 enable
BlReadEn EQU 1 ;bit13-SMBAA signal :0-1 at all time, 1-active for sync read
AddrValidReadEn EQU 1 ;bit12-SMADDRVALID signal: 0-always HIGH, 1-active for async & sync read
BurstLenRead EQU 0 ;bit1011-burst transfer length:0-4,1-8,2-16,3-cont(sync only)
SyncReadDev EQU 0 ;bit9-sync access :0-async, 1-sync
BMRead EQU 0 ;bit8-burst mode red and async page mode
SMBLSPOL EQU 0 ;bit6-polarit of signal nSMBLS
MW EQU 0 ;bit45-memory width : 00-8bit,01-16bit,10-32bit
WP EQU 0 ;bit3-write protect
WaitEn EQU 0 ;bit2-external wait signal enable
WaitPol EQU 0 ;bit1-polarity of the external wait input for actiation
RBLE EQU 0 ;bit0-read byte lane enable
SMBCR0_0 EQU ((BMRead<<8)+(SMBLSPOL<<6)+(MW<<4)+(WP<<3)+(WaitEn<<2)+(WaitPol<<1)+RBLE)
SMBCR0_1 EQU ((WrapRead<<14)+(BlReadEn<<13)+(AddrValidReadEn<<12)+(BurstLenRead<<10)+(SyncReadDev<<9))
SMBCR0_2 EQU ((BlWriteEn<<21)+(AddrValidWriteEn<<20)+(BurstLenWrite<<18)+(SyncWriteDev<<17)+(BMWrite<<16))
WaitTourErr0 EQU 0 ; external wait timeout error flag
WSTBRD0 EQU 0x1f ; burst read wait state
MemClkRatio EQU 1 ; SMMEMCLK :0-HCLK,1-HCLK/2,2-HCLK/3
SMClockEn EQU 1 ; SMCLK enable 0-only active during mem access,1-always running
ENDIF ; IF :DEF: AMDBOOT
;#########################################################################################
;#########################################################################################
_ISR_STARTADDRESS EQU 0x33ffff00
top_of_stacks EQU _ISR_STARTADDRESS
;=====================================================================================
; (42,1,1)=200Mhz, (47,1,1)=220Mhz, (72,2,1)=240Mhz, (57,1,1)=260Mhz, (125,4,1)=266Mhz
; (43,1,1)=204Mhz,
; (62,1,1)=280Mhz, (67,1,1)=300Mhz, (72,4,0)=320Mhz, (63,3,0)=340Mhz, (52,2,0)=360Mhz
; (42,1,0)=400Mhz,
; ========================================================================
; Decide Re-setting the PLL value and mem setting in Kernel.
; If 1, In Kernel the PLL will set PLL and Memory setting again.
; If 0, The kernel will not change PLL and memory,
; so The setting in Eboot will be used.
GBLA CHANGE_CLK_EBOOT
GBLA CHANGE_CLK_OAL
CHANGE_CLK_EBOOT SETA 1 ; 1:RE-Setting PLL value(refer startup.s in Eboot)
CHANGE_CLK_OAL SETA 1 ; 1:RE-Setting PLL value(refer startup.s in oal)
; ========================================================================
; PLL Value setting
; EBOOT and Kernel refers this value.
;=====================================================================================
; Fin = 12MHz,
;
; MPLLout = (2m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV, s=SDIV, Fin=10~30MHz
; (17,1,1)=300Mhz, (92,3,1)=400Mhz, (67,2,1)=450Mhz, (81,2,1)=534Mhz,
; (17,1,0)=600Mhz, (92,3,0)=800Mhz
;
; EPLLout = (m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV+2, s=SDIV, Fin=10~100MHz
; (28,1,2)=36Mhz, (40,1,2)=48Mhz, (22,1,1)=60Mhz, (28,1,1)=72Mhz, (34,1,1)=84Mhz
; (40,1,1)=96Mhz
;=====================================================================================
GBLA CLKVAL
GBLA DVSON
GBLA HCLKVAL
[ BSP_TYPE = BSP_SMDK2443
CLKVAL SETA 533
]
[ BSP_TYPE = BSP_SMDK2450
;CLKVAL SETA 533
CLKVAL SETA 400133
;CLKVAL SETA 266
;CLKVAL SETA 400
]
[ BSP_TYPE = BSP_SMDK2443
[ CLKVAL = 300
DVSON SETA 0
HCLKVAL SETA 100
Startup_MPLL EQU 300000000
Startup_Mdiv EQU 17
Startup_Pdiv EQU 1
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x2 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 400
DVSON SETA 0
HCLKVAL SETA 100
Startup_MPLL EQU 400000000
Startup_Mdiv EQU 92
Startup_Pdiv EQU 3
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x3 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 400133
DVSON SETA 0
HCLKVAL SETA 133
Startup_MPLL EQU 400000000
Startup_Mdiv EQU 92
Startup_Pdiv EQU 3
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x2 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x2 : HCLK = PREDIV_CLK/3
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 533
DVSON SETA 0
HCLKVAL SETA 133
Startup_MPLL EQU 533000000
Startup_Mdiv EQU 81
Startup_Pdiv EQU 2
Startup_Sdiv EQU 1
Startup_ARMCLKdiv EQU 0 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x1 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
[ CLKVAL = 500
DVSON SETA 0
HCLKVAL SETA 120
Startup_MPLL EQU 500000000
Startup_Mdiv EQU 34
Startup_Pdiv EQU 1
Startup_Sdiv EQU 0
Startup_ARMCLKdiv EQU 8 ; 0 : ARMCLK = MPLL/1
; 8 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 9 : ARMCLK = MPLL/4
; 10 : ARMCLK = MPLL/6
; 11 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0x3 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HCLKdiv EQU 0x1 ; 0x0 : HCLK = PREDIV_CLK
; 0x1 : HCLK = PREDIV_CLK/2
; 0x3 : HCLK = PREDIV_CLK/4
Startup_PCLKdiv EQU 1 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
]
Startup_EMdiv EQU 40 ; 96Mhz
Startup_EPdiv EQU 1
Startup_ESdiv EQU 1
]
[ BSP_TYPE = BSP_SMDK2450
[ CLKVAL = 36
DVSON SETA 0
HCLKVAL SETA 18
Startup_MPLL EQU 36000000
Startup_Mdiv EQU 24
Startup_Pdiv EQU 4
Startup_Sdiv EQU 1
Startup_ARMCLKdiv EQU 0 ; 0 : ARMCLK = MPLL/1
; 1 : ARMCLK = MPLL/2
; 2 : ARMCLK = MPLL/3
; 3 : ARMCLK = MPLL/4
; 5 : ARMCLK = MPLL/6
; 7 : ARMCLK = MPLL/8
; 13 : ARMCLK = MPLL/12
; 15 : ARMCLK = MPLL/16
Startup_PREdiv EQU 0 ; 0x0 : PREDIV_CLK = MPLL
; 0x1 : PREDIV_CLK = MPLL/2
; 0x2 : PREDIV_CLK = MPLL/3
; 0x3 : PREDIV_CLK = MPLL/4
Startup_HALFHCLKdiv EQU 1 ; 0 : HCLKx1_2(SSMC) = HCLK
; 1 : HCLKx1_2(SSMC) = HCLK/2
Startup_PCLKdiv EQU 0 ; 0 : PCLK = HCLK
; 1 : PCLK = HCLK/2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -