📄 s3c6410otgdevice.h
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#define DIEPTSIZ13 0xAB0 // Device IN Endpoint 13 Transfer Size
#define DOEPTSIZ13 0xCB0 // Device OUT Endpoint 13 Transfer Size
#define DIEPDMA13 0xAB4 // Device IN Endpoint 13 DMA Address
#define DOEPDMA13 0xCB4 // Device OUT Endpoint 13 DMA Address
#define DIEPCTL14 0xAC0 // Device IN Endpoint 14 Control
#define DOEPCTL14 0xCC0 // Device OUT Endpoint 14 Control
#define DIEPINT14 0xAC8 // Device IN Endpoint 14 Interrupt
#define DOEPINT14 0xCC8 // Device OUT Endpoint 14 Interrupt
#define DIEPTSIZ14 0xAD0 // Device IN Endpoint 14 Transfer Size
#define DOEPTSIZ14 0xCD0 // Device OUT Endpoint 14 Transfer Size
#define DIEPDMA14 0xAD4 // Device IN Endpoint 14 DMA Address
#define DOEPDMA14 0xCD4 // Device OUT Endpoint 14 DMA Address
#define DIEPCTL15 0xAE0 // Device IN Endpoint 15 Control
#define DOEPCTL15 0xCE0 // Device OUT Endpoint 15 Control
#define DIEPINT15 0x9E8 // Device IN Endpoint 15 Interrupt
#define DOEPINT15 0xCE8 // Device OUT Endpoint 15 Interrupt
#define DIEPTSIZ15 0x9F0 // Device IN Endpoint 15 Transfer Size
#define DOEPTSIZ15 0xCF0 // Device OUT Endpoint 15 Transfer Size
#define DIEPDMA15 0x9F4 // Device IN Endpoint 15 DMA Address
#define DOEPDMA15 0xCF4 // Device OUT Endpoint 15 DMA Address
//////////////////////////////////////////////////////////////////////////////////////////
#define EP0_FIFO 0x1000
#define EP1_FIFO 0x2000
#define EP2_FIFO 0x3000
#define EP3_FIFO 0x4000
#define EP4_FIFO 0x5000
#define EP5_FIFO 0x6000
#define EP6_FIFO 0x7000
#define EP7_FIFO 0x8000
#define EP8_FIFO 0x9000
#define EP9_FIFO 0xa000
#define EP10_FIFO 0xb000
#define EP11_FIFO 0xc000
#define EP12_FIFO 0xd000
#define EP13_FIFO 0xe000
#define EP14_FIFO 0xf000
#define EP15_FIFO 0x10000
#define BASE_REGISTER_OFFSET 0x0
// Can be used for Interrupt and Interrupt Enable Reg - common bit def
#define EP0_IN_INT (0x1<<0)
#define EP1_IN_INT (0x1<<1)
#define EP2_IN_INT (0x1<<2)
#define EP3_IN_INT (0x1<<3)
#define EP4_IN_INT (0x1<<4)
#define EP5_IN_INT (0x1<<5)
#define EP6_IN_INT (0x1<<6)
#define EP7_IN_INT (0x1<<7)
#define EP8_IN_INT (0x1<<8)
#define EP9_IN_INT (0x1<<9)
#define EP10_IN_INT (0x1<<10)
#define EP11_IN_INT (0x1<<11)
#define EP12_IN_INT (0x1<<12)
#define EP13_IN_INT (0x1<<13)
#define EP14_IN_INT (0x1<<14)
#define EP15_IN_INT (0x1<<15)
#define EP0_OUT_INT (0x1<<16)
#define EP1_OUT_INT (0x1<<17)
#define EP2_OUT_INT (0x1<<18)
#define EP3_OUT_INT (0x1<<19)
#define EP4_OUT_INT (0x1<<20)
#define EP5_OUT_INT (0x1<<21)
#define EP6_OUT_INT (0x1<<22)
#define EP7_OUT_INT (0x1<<23)
#define EP8_OUT_INT (0x1<<24)
#define EP9_OUT_INT (0x1<<25)
#define EP10_OUT_INT (0x1<<26)
#define EP11_OUT_INT (0x1<<27)
#define EP12_OUT_INT (0x1<<28)
#define EP13_OUT_INT (0x1<<29)
#define EP14_OUT_INT (0x1<<30)
#define EP15_OUT_INT (0x1<<31)
// GOTGINT
#define SesEndDet (0x1<<2)
// GUSBCFG
#define EXTERNAL_48MCLK (0x1<<15) // PHY Low-Power Clock Select 0:480Mhz Internall PLL clock, 1:48Mhz External clock
#define NP_TXFIFO_REWIND_EN (0x1<<14)
#define TURNAROUND_TIME (0x3<<10)
#define HNP_EN (0x1<<9)
#define SRP_EN (0x1<<8)
#define PHYIF_16BIT (0x1<<3) // PHY Interface 0:8bit, 1:16bit
#define HS_FS_TIMEOUT (0) // [2:0] HS/FS Timeout Calibration
// GRSTCTL
#define AHBIDLE (0x1<<31) // AHB Master IDLE
#define TXFFLSH (0x1<<5) // TxFIFO Flush
#define RXFFLSH (0x1<<4) // RxFIFO Flush
#define INTKNQFLSH (0x1<<3) // IN Token Sequence Learning Queue Flush
#define FRMCNTRRST (0x1<<2) // Host Frame Counter Reset
#define HSFTRST (0x1<<1) // Hclk Soft Reset
#define CSFTRST (0x1<<0) // Core Soft Reset
// GINTSTS core interrupt register
#define INT_RESUME (0x1<<31)
#define INT_SSREQ (0x1<<30)
#define INT_DISCONN (0x1<<29)
#define INT_OUT_EP (0x1<<19)
#define INT_IN_EP (0x1<<18)
#define INT_EPMIS (0x1<<17)
#define INT_SDE (0x1<<13)
#define INT_RESET (0x1<<12)
#define INT_SUSPEND (0x1<<11)
#define INT_TX_FIFO_EMPTY (0x1<<5)
#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
#define INT_SOF (0x1<<3)
#define INT_OTG (0x1<<2)
// GRXSTSP & GRXSTSR
#define PACKET_STATUS_MSK (0xf<<17)
#define PACKET_STATUS_IDX (17)
#define PKTSTS_GOUTNAK (0x1)
#define BYTE_COUNT_MSK (0x7ff0)
#define BYTE_COUNT_IDX (4)
#define EPNUM_MSK (0xf)
// GAHBCFG
#define NPTXFEMPLVL_COMPLETE_EMPTY (1<<7)
#define MODE_DMA (1<<5)
#define MODE_SLAVE (0<<5)
#define BURST_SINGLE (0<<1)
#define BURST_INCR (1<<1)
#define BURST_INCR4 (3<<1)
#define BURST_INCR8 (5<<1)
#define BURST_INCR16 (7<<1)
#define GBL_INT_MASK (0<<0)
#define GBL_INT_UNMASK (1<<0)
// GOTGCTL
#define B_SESSION_VALID (0x1<<19)
#define A_SESSION_VALID (0x1<<18)
#define SESSION_REQUEST (0x1<<1) // 0:No session request, 1:Session request
// GRX STATUS
#define PKTSTS (0xF<<17)
#define GLOBAL_OUT_NAK (0x1<<17)
#define OUT_PKT_RECEIVED (0x2<<17)
#define OUT_TRF_COMPLETED (0x3<<17)
#define SETUP_TRANS_COMPLETED (0x4<<17)
#define SETUP_PKT_RECEIVED (0x6<<17)
#define SETUPPHASEDONE (0x1<<3) //Setup Phase Done Interrupt
#define XFERCOPMPL (0x1<<0) //Transfer Complete Interrupt
// GRXFSIZ
#define RXFIFO_DEPTH (0x800)
// GNPTXFSIZ
#define NPTXFIFO_DEPTH (0x800)
#define NPTXFIFO_DEPTH_IDX (16) // [31:16] Non-Periodic TxFIFO Depth
// DCFG
#define IN_EP_MISS_CNT_IDX (18) // [22:18] IN Endpoint Mismatch Count
#define DEVICE_ADDRESS_MSK (0x7F<<4) // [10:4] Device Address
#define DEVICE_SPEED_HIGH (0x0<<0) // [1:0] High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
#define DEVICE_SPEED_FULL (0x1<<0) // [1:0] Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
// DIEPCTL/DOEPCTL device control IN/OUT endpoint control register
#define EP_ENABLE (0x1<<31)
#define EP_DISABLE (0x1<<30)
#define SET_D0_PID (0x1<<28)
#define SET_NAK (0x1<<27)
#define CLEAR_NAK (0x1<<26)
#define STALL (0x1<<21)
#define EPTYPE (0x3<<18)
#define SET_TYPE_CONTROL (0x0<<18)
#define SET_TYPE_ISO (0x1<<18)
#define SET_TYPE_BULK (0x2<<18)
#define SET_TYPE_INTERRUPT (0x3<<18)
#define USB_ACT_EP (0x1<<15)
#define NEXT_EP_IDX (11)
#define EP0_MAX_PK_SIZ (0x0<<0) // [1:0] 0:64byte, 1:32byte, 2:16byte, 3:8byte
// DIEPINT
#define IN_TKN_RECEIVED (0x1<<4)
#define TIMEOUT_CONDITION (0x1<<3)
#define XFER_COMPLETE (0x1<<0)
// DOEPINT
#define SETUP_PHASE_DONE (0x1<<3)
// DOEPTSIZ , DIEPTSIZ
#define SETUP_PKT_CNT_IDX (29)
#define MULTI_CNT_IDX (29)
#define PACKET_COUTNT_IDX (19)
// DCTL
#define CLEAR_GOUTNAK (0x1<<10)
#define SET_GOUTNAK (0x1<<9)
#define CLEAR_GNPINNAK (0x1<<8)
#define SET_GNINNAK (0x1<<7)
#define SOFT_DISCONNECT (0x1<<1)
#define RMTWKUPSIG (0x1<<0)
// DSTS
#define ENUM_SPEED_MSK (0x6)
// SYSCON - HCLK GATE
#define OTG_HCLK_EN (1<<20)
// SYSCON - OTHERS
#define USB_SIG_MASK (1<<16)
#define IN_EP 0
#define OUT_EP 1
/////////////////////////////////////////////
#define IN_TRANSFER 1
#define OUT_TRANSFER 2
enum EP0_STATE {
EP0_STATE_IDLE = 0,
EP0_STATE_IN_DATA_PHASE,
EP0_STATE_OUT_DATA_PHASE
};
typedef enum
{
USB_HIGH, USB_FULL, USB_LOW
} USB_SPEED;
typedef struct EP_STATUS {
DWORD dwEndpointNumber;
DWORD dwDirectionAssigned;
DWORD dwPacketSizeAssigned;
BOOL bInitialized;
DWORD dwEndpointType;
PSTransfer pTransfer;
CRITICAL_SECTION cs;
} *PEP_STATUS;
typedef enum
{
USB_RNDIS = 0,
USB_SERIAL,
USB_MSF
};
#endif //_S3C6410OTGD_H_
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