📄 s3c6410otgdevice.h
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#define HCDMA4 0x594 // Host Channel-4 DMA Address
// Host Channel-Specific Registers #5
#define HCCHAR5 0x5A0 // Host Channel-5 Characteristics
#define HCSPLT5 0x5A4 // Host Channel-5 Split Control
#define HCINT5 0x5A8 // Host Channel-5 Interrupt
#define HCINTMSK5 0x5AC // Host Channel-5 Interrupt Mask
#define HCTSIZ5 0x5B0 // Host Channel-5 Transfer Size
#define HCDMA5 0x5B4 // Host Channel-5 DMA Address
// Host Channel-Specific Registers #6
#define HCCHAR6 0x5C0 // Host Channel-6 Characteristics
#define HCSPLT6 0x5C4 // Host Channel-6 Split Control
#define HCINT6 0x5C8 // Host Channel-6 Interrupt
#define HCINTMSK6 0x5CC // Host Channel-6 Interrupt Mask
#define HCTSIZ6 0x5D0 // Host Channel-6 Transfer Size
#define HCDMA6 0x5D4 // Host Channel-6 DMA Address
// Host Channel-Specific Registers #7
#define HCCHAR7 0x5E0 // Host Channel-7 Characteristics
#define HCSPLT7 0x5E4 // Host Channel-7 Split Control
#define HCINT7 0x5E8 // Host Channel-7 Interrupt
#define HCINTMSK7 0x5EC // Host Channel-7 Interrupt Mask
#define HCTSIZ7 0x5F0 // Host Channel-7 Transfer Size
#define HCDMA7 0x5F4 // Host Channel-7 DMA Address
// Host Channel-Specific Registers #8
#define HCCHAR8 0x600 // Host Channel-8 Characteristics
#define HCSPLT8 0x604 // Host Channel-8 Split Control
#define HCINT8 0x608 // Host Channel-8 Interrupt
#define HCINTMSK8 0x60C // Host Channel-8 Interrupt Mask
#define HCTSIZ8 0x610 // Host Channel-8 Transfer Size
#define HCDMA8 0x614 // Host Channel-8 DMA Address
// Host Channel-Specific Registers #9
#define HCCHAR9 0x620 // Host Channel-9 Characteristics
#define HCSPLT9 0x624 // Host Channel-9 Split Control
#define HCINT9 0x628 // Host Channel-9 Interrupt
#define HCINTMSK9 0x62C // Host Channel-9 Interrupt Mask
#define HCTSIZ9 0x630 // Host Channel-9 Transfer Size
#define HCDMA9 0x634 // Host Channel-9 DMA Address
// Host Channel-Specific Registers #10
#define HCCHAR10 0x640 // Host Channel-10 Characteristics
#define HCSPLT10 0x644 // Host Channel-10 Split Control
#define HCINT10 0x648 // Host Channel-10 Interrupt
#define HCINTMSK10 0x64C // Host Channel-10 Interrupt Mask
#define HCTSIZ10 0x650 // Host Channel-10 Transfer Size
#define HCDMA10 0x654 // Host Channel-10 DMA Address
// Host Channel-Specific Registers #11
#define HCCHAR11 0x660 // Host Channel-11 Characteristics
#define HCSPLT11 0x664 // Host Channel-11 Split Control
#define HCINT11 0x668 // Host Channel-11 Interrupt
#define HCINTMSK11 0x66C // Host Channel-11 Interrupt Mask
#define HCTSIZ11 0x670 // Host Channel-11 Transfer Size
#define HCDMA11 0x674 // Host Channel-11 DMA Address
// Host Channel-Specific Registers #12
#define HCCHAR12 0x680 // Host Channel-12 Characteristics
#define HCSPLT12 0x684 // Host Channel-12 Split Control
#define HCINT12 0x688 // Host Channel-12 Interrupt
#define HCINTMSK12 0x68C // Host Channel-12 Interrupt Mask
#define HCTSIZ12 0x690 // Host Channel-12 Transfer Size
#define HCDMA12 0x694 // Host Channel-12 DMA Address
// Host Channel-Specific Registers #13
#define HCCHAR13 0x6A0 // Host Channel-13 Characteristics
#define HCSPLT13 0x6A4 // Host Channel-13 Split Control
#define HCINT13 0x6A8 // Host Channel-13 Interrupt
#define HCINTMSK13 0x6AC // Host Channel-13 Interrupt Mask
#define HCTSIZ13 0x6B0 // Host Channel-13 Transfer Size
#define HCDMA13 0x6B4 // Host Channel-13 DMA Address
// Host Channel-Specific Registers #14
#define HCCHAR14 0x6C0 // Host Channel-14 Characteristics
#define HCSPLT14 0x6C4 // Host Channel-14 Split Control
#define HCINT14 0x6C8 // Host Channel-14 Interrupt
#define HCINTMSK14 0x6CC // Host Channel-14 Interrupt Mask
#define HCTSIZ14 0x6D0 // Host Channel-14 Transfer Size
#define HCDMA14 0x6D4 // Host Channel-14 DMA Address
// Host Channel-Specific Registers #15
#define HCCHAR15 0x680 // Host Channel-15 Characteristics
#define HCSPLT15 0x684 // Host Channel-15 Split Control
#define HCINT15 0x688 // Host Channel-15 Interrupt
#define HCINTMSK15 0x68C // Host Channel-15 Interrupt Mask
#define HCTSIZ15 0x690 // Host Channel-15 Transfer Size
#define HCDMA15 0x694 // Host Channel-15 DMA Address
//*********************************************************************
// Device Mode Registers
//*********************************************************************
// Device Global Registers
#define DCFG 0x800 // Device Configuration
#define DCTL 0x804 // Device Control
#define DSTS 0x808 // Device Status
#define DIEPMSK 0x810 // Device IN Endpoint Common Interrupt Mask
#define DOEPMSK 0x814 // Device OUT Endpoint Common Interrupt Mask
#define DAINT 0x818 // Device All Endpoints Interrupt
#define DAINTMSK 0x81C // Device All Endpoints Interrupt Mask
#define DTKNQR1 0x820 // Device IN Token Sequence Learning Queue Read 1
#define DTKNQR2 0x824 // Device IN Token Sequence Learning Queue Read 2
#define DVBUSDIS 0x828 // Device VBUS Discharge Time
#define DVBUSPULSE 0x82C // Device VBUS Pulsing Time
#define DTKNQR3 0x830 // Device IN Token Sequence Learning Queue Read 3
#define DTKNQR4 0x834 // Device IN Token Sequence Learning Queue Read 4
#define DIEPCTL 0x900 // Device IN Endpoint 0 Control
#define DOEPCTL 0xB00 // Device OUT Endpoint 0 Control
#define DIEPINT 0x908 // Device IN Endpoint 0 Interrupt
#define DOEPINT 0xB08 // Device OUT Endpoint 0 Interrupt
#define DIEPTSIZ 0x910 // Device IN Endpoint 0 Transfer Size
#define DOEPTSIZ 0xB10 // Device OUT Endpoint 0 Transfer Size
#define DIEPDMA 0x914 // Device IN Endpoint 0 DMA Address
#define DOEPDMA 0xB14 // Device OUT Endpoint 0 DMA Address
// Device Logical Endpoints-Specific Registers
#define DIEPCTL0 0x900 // Device IN Endpoint 0 Control
#define DOEPCTL0 0xB00 // Device OUT Endpoint 0 Control
#define DIEPINT0 0x908 // Device IN Endpoint 0 Interrupt
#define DOEPINT0 0xB08 // Device OUT Endpoint 0 Interrupt
#define DIEPTSIZ0 0x910 // Device IN Endpoint 0 Transfer Size
#define DOEPTSIZ0 0xB10 // Device OUT Endpoint 0 Transfer Size
#define DIEPDMA0 0x914 // Device IN Endpoint 0 DMA Address
#define DOEPDMA0 0xB14 // Device OUT Endpoint 0 DMA Address
#define DIEPCTL1 0x920 // Device IN Endpoint 1 Control
#define DOEPCTL1 0xB20 // Device OUT Endpoint 1 Control
#define DIEPINT1 0x928 // Device IN Endpoint 1 Interrupt
#define DOEPINT1 0xB28 // Device OUT Endpoint 1 Interrupt
#define DIEPTSIZ1 0x930 // Device IN Endpoint 1 Transfer Size
#define DOEPTSIZ1 0xB30 // Device OUT Endpoint 1 Transfer Size
#define DIEPDMA1 0x934 // Device IN Endpoint 1 DMA Address
#define DOEPDMA1 0xB34 // Device OUT Endpoint 1 DMA Address
#define DIEPCTL2 0x940 // Device IN Endpoint 2 Control
#define DOEPCTL2 0xB40 // Device OUT Endpoint 2 Control
#define DIEPINT2 0x948 // Device IN Endpoint 2 Interrupt
#define DOEPINT2 0xB48 // Device OUT Endpoint 2 Interrupt
#define DIEPTSIZ2 0x950 // Device IN Endpoint 2 Transfer Size
#define DOEPTSIZ2 0xB50 // Device OUT Endpoint 2 Transfer Size
#define DIEPDMA2 0x954 // Device IN Endpoint 2 DMA Address
#define DOEPDMA2 0xB54 // Device OUT Endpoint 2 DMA Address
#define DIEPCTL3 0x960 // Device IN Endpoint 3 Control
#define DOEPCTL3 0xB60 // Device OUT Endpoint 3 Control
#define DIEPINT3 0x968 // Device IN Endpoint 3 Interrupt
#define DOEPINT3 0xB68 // Device OUT Endpoint 3 Interrupt
#define DIEPTSIZ3 0x970 // Device IN Endpoint 3 Transfer Size
#define DOEPTSIZ3 0xB70 // Device OUT Endpoint 3 Transfer Size
#define DIEPDMA3 0x974 // Device IN Endpoint 3 DMA Address
#define DOEPDMA3 0xB74 // Device OUT Endpoint 3 DMA Address
#define DIEPCTL4 0x980 // Device IN Endpoint 4 Control
#define DOEPCTL4 0xB80 // Device OUT Endpoint 4 Control
#define DIEPINT4 0x988 // Device IN Endpoint 4 Interrupt
#define DOEPINT4 0xB88 // Device OUT Endpoint 4 Interrupt
#define DIEPTSIZ4 0x990 // Device IN Endpoint 4 Transfer Size
#define DOEPTSIZ4 0xB90 // Device OUT Endpoint 4 Transfer Size
#define DIEPDMA4 0x994 // Device IN Endpoint 4 DMA Address
#define DOEPDMA4 0xB94 // Device OUT Endpoint 4 DMA Address
#define DIEPCTL5 0x9A0 // Device IN Endpoint 5 Control
#define DOEPCTL5 0xBA0 // Device OUT Endpoint 5 Control
#define DIEPINT5 0x9A8 // Device IN Endpoint 5 Interrupt
#define DOEPINT5 0xBA8 // Device OUT Endpoint 5 Interrupt
#define DIEPTSIZ5 0x9B0 // Device IN Endpoint 5 Transfer Size
#define DOEPTSIZ5 0xBB0 // Device OUT Endpoint 5 Transfer Size
#define DIEPDMA5 0x9B4 // Device IN Endpoint 5 DMA Address
#define DOEPDMA5 0xBB4 // Device OUT Endpoint 5 DMA Address
#define DIEPCTL6 0x9C0 // Device IN Endpoint 6 Control
#define DOEPCTL6 0xBC0 // Device OUT Endpoint 6 Control
#define DIEPINT6 0x9C8 // Device IN Endpoint 6 Interrupt
#define DOEPINT6 0xBC8 // Device OUT Endpoint 6 Interrupt
#define DIEPTSIZ6 0x9D0 // Device IN Endpoint 6 Transfer Size
#define DOEPTSIZ6 0xBD0 // Device OUT Endpoint 6 Transfer Size
#define DIEPDMA6 0x9D4 // Device IN Endpoint 6 DMA Address
#define DOEPDMA6 0xBD4 // Device OUT Endpoint 6 DMA Address
#define DIEPCTL7 0x9E0 // Device IN Endpoint 7 Control
#define DOEPCTL7 0xBE0 // Device OUT Endpoint 7 Control
#define DIEPINT7 0x9E8 // Device IN Endpoint 7 Interrupt
#define DOEPINT7 0xBE8 // Device OUT Endpoint 7 Interrupt
#define DIEPTSIZ7 0x9F0 // Device IN Endpoint 7 Transfer Size
#define DOEPTSIZ7 0xBF0 // Device OUT Endpoint 7 Transfer Size
#define DIEPDMA7 0x9F4 // Device IN Endpoint 7 DMA Address
#define DOEPDMA7 0xBF4 // Device OUT Endpoint 7 DMA Address
#define DIEPCTL8 0xA00 // Device IN Endpoint 8 Control
#define DOEPCTL8 0xC00 // Device OUT Endpoint 8 Control
#define DIEPINT8 0xA08 // Device IN Endpoint 8 Interrupt
#define DOEPINT8 0xC08 // Device OUT Endpoint 8 Interrupt
#define DIEPTSIZ8 0xA10 // Device IN Endpoint 8 Transfer Size
#define DOEPTSIZ8 0xC10 // Device OUT Endpoint 8 Transfer Size
#define DIEPDMA8 0xA14 // Device IN Endpoint 8 DMA Address
#define DOEPDMA8 0xC14 // Device OUT Endpoint 8 DMA Address
#define DIEPCTL9 0xA20 // Device IN Endpoint 9 Control
#define DOEPCTL9 0xC20 // Device OUT Endpoint 9 Control
#define DIEPINT9 0xA28 // Device IN Endpoint 9 Interrupt
#define DOEPINT9 0xC28 // Device OUT Endpoint 9 Interrupt
#define DIEPTSIZ9 0xA30 // Device IN Endpoint 9 Transfer Size
#define DOEPTSIZ9 0xC30 // Device OUT Endpoint 9 Transfer Size
#define DIEPDMA9 0xA34 // Device IN Endpoint 9 DMA Address
#define DOEPDMA9 0xC34 // Device OUT Endpoint 9 DMA Address
#define DIEPCTL10 0xA40 // Device IN Endpoint 10 Control
#define DOEPCTL10 0xC40 // Device OUT Endpoint 10 Control
#define DIEPINT10 0xA48 // Device IN Endpoint 10 Interrupt
#define DOEPINT10 0xC48 // Device OUT Endpoint 10 Interrupt
#define DIEPTSIZ10 0xA50 // Device IN Endpoint 10 Transfer Size
#define DOEPTSIZ10 0xC50 // Device OUT Endpoint 10 Transfer Size
#define DIEPDMA10 0xA54 // Device IN Endpoint 10 DMA Address
#define DOEPDMA10 0xC54 // Device OUT Endpoint 10 DMA Address
#define DIEPCTL11 0xA60 // Device IN Endpoint 11 Control
#define DOEPCTL11 0xC60 // Device OUT Endpoint 11 Control
#define DIEPINT11 0xA68 // Device IN Endpoint 11 Interrupt
#define DOEPINT11 0xC68 // Device OUT Endpoint 11 Interrupt
#define DIEPTSIZ11 0xA70 // Device IN Endpoint 11 Transfer Size
#define DOEPTSIZ11 0xC70 // Device OUT Endpoint 11 Transfer Size
#define DIEPDMA11 0xA74 // Device IN Endpoint 11 DMA Address
#define DOEPDMA11 0xC74 // Device OUT Endpoint 11 DMA Address
#define DIEPCTL12 0xA80 // Device IN Endpoint 12 Control
#define DOEPCTL12 0xC80 // Device OUT Endpoint 12 Control
#define DIEPINT12 0xA88 // Device IN Endpoint 12 Interrupt
#define DOEPINT12 0xC88 // Device OUT Endpoint 12 Interrupt
#define DIEPTSIZ12 0xA90 // Device IN Endpoint 12 Transfer Size
#define DOEPTSIZ12 0xC90 // Device OUT Endpoint 12 Transfer Size
#define DIEPDMA12 0xA94 // Device IN Endpoint 12 DMA Address
#define DOEPDMA12 0xC94 // Device OUT Endpoint 12 DMA Address
#define DIEPCTL13 0xAA0 // Device IN Endpoint 13 Control
#define DOEPCTL13 0xCA0 // Device OUT Endpoint 13 Control
#define DIEPINT13 0xAA8 // Device IN Endpoint 13 Interrupt
#define DOEPINT13 0xCA8 // Device OUT Endpoint 13 Interrupt
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