📄 atapi2.h
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#define MWDMA_MODE0_CYCLE_TIME 480
#define MWDMA_MODE1_CYCLE_TIME 150
#define MWDMA_MODE2_CYCLE_TIME 120
#define UDMA_MODE0_CYCLE_TIME 120
#define UDMA_MODE1_CYCLE_TIME 80
#define UDMA_MODE2_CYCLE_TIME 60
#define UDMA_MODE3_CYCLE_TIME 45
#define UDMA_MODE4_CYCLE_TIME 30
//
// IDENTIFY DMA timing cycle modes.
//
#define UNINITIALIZED_CYCLE_TIME 0xffffffff
#define UNINITIALIZED_TRANSFER_MODE 0xffffffff
#define IDENTIFY_DMA_CYCLES_MODE_0 0x00
#define IDENTIFY_DMA_CYCLES_MODE_1 0x01
#define IDENTIFY_DMA_CYCLES_MODE_2 0x02
//
// Identify Data General Configuration Bit Definition
//
#define IDE_IDDATA_DEVICE_TYPE_MASK ((1 << 15) | (1 << 14))
#define IDE_IDDATA_ATAPI_DEVICE (1 << 15)
#define IDE_IDDATA_ATAPI_DEVICE_MASK ((1 << 12) | (1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
#define IDE_IDDATA_REMOVABLE (1 << 7)
#define IDE_IDDATA_DRQ_TYPE_MASK ((1 << 6) | (1 << 5))
#define IDE_IDDATA_INTERRUPT_DRQ ((1 << 6) | (0 << 5))
//
// Peripheral Device Types
//
#define ATA_IDDEVICE_DISK 0 // DIRECT ACCESS DEVICE
#define ATA_IDDEVICE_CDROM 5
#define ATA_IDDEVICE_OPTICAL_MEM 7
#define ATA_IDDEVICE_UNKNOWN 0x1F
#define PIO_MODE2 (1 << 2)
#define PIO_MODE3 (1 << 3)
#define PIO_MODE4 (1 << 4)
#define SWDMA_MODE0 (1 << 5)
#define SWDMA_MODE1 (1 << 6)
#define SWDMA_MODE2 (1 << 7)
#define MWDMA_MODE0 (1 << 8)
#define PIO_MODE0 (1 << 0)
#define PIO_MODE1 (1 << 1)
#define MWDMA_MODE1 (1 << 9)
#define MWDMA_MODE2 (1 << 10)
#define UDMA_MODE0 (1 << 11)
#define UDMA_MODE1 (1 << 12)
#define UDMA_MODE2 (1 << 13)
#define UDMA_MODE3 (1 << 14)
#define UDMA_MODE4 (1 << 15)
#define PIO_SUPPORT (PIO_MODE0 | PIO_MODE1 | PIO_MODE2 | PIO_MODE3 | PIO_MODE4)
#define SWDMA_SUPPORT (SWDMA_MODE0 | SWDMA_MODE1 | SWDMA_MODE2)
#define MWDMA_SUPPORT (MWDMA_MODE0 | MWDMA_MODE1 | MWDMA_MODE2)
#define UDMA33_SUPPORT (UDMA_MODE0 | UDMA_MODE1 | UDMA_MODE2)
#define UDMA66_SUPPORT (UDMA_MODE3 | UDMA_MODE4)
#define UDMA_SUPPORT (UDMA33_SUPPORT | UDMA66_SUPPORT )
#define DMA_SUPPORT (SWDMA_SUPPORT | MWDMA_SUPPORT | UDMA_SUPPORT)
#define ALL_MODE_SUPPORT (PIO_SUPPORT | DMA_SUPPORT)
//
// ID DATA
//
#define IDD_UDMA_MODE0_ACTIVE (1 << 0)
#define IDD_UDMA_MODE1_ACTIVE (1 << 1)
#define IDD_UDMA_MODE2_ACTIVE (1 << 2)
#define IDD_UDMA_MODE3_ACTIVE (1 << 3)
#define IDD_UDMA_MODE4_ACTIVE (1 << 4)
#define IDD_MWDMA_MODE0_ACTIVE (1 << 0)
#define IDD_MWDMA_MODE1_ACTIVE (1 << 1)
#define IDD_MWDMA_MODE2_ACTIVE (1 << 2)
#define IDD_SWDMA_MODE0_ACTIVE (1 << 0)
#define IDD_SWDMA_MODE1_ACTIVE (1 << 1)
#define IDD_SWDMA_MODE2_ACTIVE (1 << 2)
#define IDD_UDMA_MODE0_SUPPORTED (1 << 0)
#define IDD_UDMA_MODE1_SUPPORTED (1 << 1)
#define IDD_UDMA_MODE2_SUPPORTED (1 << 2)
#define IDD_MWDMA_MODE0_SUPPORTED (1 << 0)
#define IDD_MWDMA_MODE1_SUPPORTED (1 << 1)
#define IDD_MWDMA_MODE2_SUPPORTED (1 << 2)
#define IDD_SWDMA_MODE0_SUPPORTED (1 << 0)
#define IDD_SWDMA_MODE1_SUPPORTED (1 << 1)
#define IDD_SWDMA_MODE2_SUPPORTED (1 << 2)
//
// Beautification macros
//
// IDENTIFY capability bit definitions.
//
#define IDENTIFY_CAPABILITIES_DMA_SUPPORTED (1 << 8)
#define IDENTIFY_CAPABILITIES_LBA_SUPPORTED (1 << 9)
#define IDENTIFY_CAPABILITIES_IOREADY_CAN_BE_DISABLED (1 << 10)
#define IDENTIFY_CAPABILITIES_IOREADY_SUPPORTED (1 << 11)
//
// Command set bit definitions
//
#define IDENTIFY_COMMAND_SET_POWER_MANAGEMENT (1 << 3)
#define IDENTIFY_COMMAND_SET_WRITE_CACHE (1 << 5)
//
// Command set supported bit definitions
//
#define COMMAND_SET_WRITE_CACHE_SUPPORTED IDENTIFY_COMMAND_SET_WRITE_CACHE
#define COMMAND_SET_POWER_MANAGEMENT_SUPPORTED IDENTIFY_COMMAND_SET_POWER_MANAGEMENT
//
// Command set enabled bit definitions
//
#define COMMAND_SET_WRITE_CACHE_ENABLED IDENTIFY_COMMAND_SET_WRITE_CACHE
#define COMMAND_SET_POWER_MANAGEMENT_ENABLED IDENTIFY_COMMAND_SET_POWER_MANAGEMENT
//
// This command causes all members of the following structure to be stored in packed
// stored in packedform e.i without extra space for alignment.
//
//
// ATA/ATAPI-6 definition of IDENTIFY_DEVICE results with 48-bit LBA support.
//
#pragma pack(1)
typedef struct _IDENTIFY_DATA {
USHORT GeneralConfiguration; // 00 Mandatory for ATAPI
USHORT NumberOfCylinders; // 01 Not used for ATAPI
USHORT Reserved1; // 02 Not used for ATAPI
USHORT NumberOfHeads; // 03 Not used for ATAPI
USHORT UnformattedBytesPerTrack; // 04 Not used for ATAPI
USHORT UnformattedBytesPerSector; // 05 Not used for ATAPI
USHORT SectorsPerTrack; // 06 Not used for ATAPI
USHORT VendorUnique1[3]; // 07-09 Not used for ATAPI
USHORT SerialNumber[10]; // 10 Optional for ATAPI
USHORT BufferType; // 20 Not used for ATAPI
USHORT BufferSectorSize; // 21 Not used for ATAPI
USHORT NumberOfEccBytes; // 22 Not used for ATAPI
USHORT FirmwareRevision[4]; // 23 Mandatory for ATAPI
USHORT ModelNumber[20]; // 27 Mandatory for ATAPI
UCHAR MaximumBlockTransfer; // 47 low byte Not used for ATAPI
UCHAR VendorUnique2; // 47 high byte Not used for ATAPI
USHORT DoubleWordIo; // 48 Not used for ATAPI
USHORT Capabilities; // 49 Mandatory for ATAPI
USHORT Capabilities2; // 50 bit 0 = 1 to indicate a device specific Standby timer value minimum
UCHAR VendorUnique3; // 51 low byte Mandatory for ATAPI
UCHAR PioCycleTimingMode; // 51 high byte Mandatory for ATAPI
UCHAR VendorUnique4; // 52 low byte Mandatory for ATAPI
UCHAR DmaCycleTimingMode; // 52 high byte Mandatory for ATAPI
USHORT TranslationFieldsValid; // 53 (low bit) Mandatory for ATAPI
USHORT NumberOfCurrentCylinders; // 54 Not used for ATAPI
USHORT NumberOfCurrentHeads; // 55 Not used for ATAPI
USHORT CurrentSectorsPerTrack; // 56 Not used for ATAPI
ULONG CurrentSectorCapacity; // 57 & 58 Not used for ATAPI
UCHAR MultiSectorCount; // 59 low Not used for ATAPI
UCHAR MultiSectorSettingValid; // 59 high (low bit)Not used for ATAPI
ULONG TotalUserAddressableSectors; // 60 & 61 Not used for ATAPI
UCHAR SingleDmaModesSupported; // 62 low byte Mandatory for ATAPI
UCHAR SingleDmaTransferActive; // 62 high byte Mandatory for ATAPI
UCHAR MultiDmaModesSupported; // 63 low byte Mandatory for ATAPI
UCHAR MultiDmaTransferActive; // 63 high byte Mandatory for ATAPI
UCHAR AdvancedPIOxferreserved; // 64 low byte Mandatory for ATAPI
UCHAR AdvancedPIOxfer; // 64 high byte Mandatory for ATAPI
USHORT MinimumMultiwordDMATime; // 65 Mandatory for ATAPI
USHORT ManuRecomendedDMATime; // 66 Mandatory for ATAPI
USHORT MinimumPIOxferTimeWOFlow; // 67 Mandatory for ATAPI
USHORT MinimumPIOxferTimeIORDYFlow; // 68 Mandatory for ATAPI
USHORT ReservedADVPIOSupport[2]; // 69 Not used for ATAPI
USHORT TypicalProcTimeForOverlay; // 71 Optional for ATAPI
USHORT TypicalRelTimeForOverlay; // 72 Optional for ATAPI
USHORT MajorRevisionNumber; // 73 Optional for ATAPI
USHORT MinorRevisionNumber; // 74 Optional for ATAP
USHORT QueueDepth; // 75
USHORT Reserved6[4]; // 76-79
USHORT MajorVersionNumber; // 80
USHORT MinorVersionNumber; // 81
USHORT CommandSetSupported1; // 82
USHORT CommandSetSupported2; // 83
USHORT CommandSetFeaturesSupported; // 84
USHORT CommandSetFeatureEnabled1; // 85
USHORT CommandSetFeatureEnabled2; // 86
USHORT CommandSetFeatureDefault ; // 87
UCHAR UltraDMASupport; // 88 Low
UCHAR UltraDMAActive; // 88 High
USHORT TimeRequiredForSecurityErase; // 89 Time Required For Security Erase Unit Completion
USHORT TimeReuiregForEnhancedSecurtity; // 90 Time Required For Enhanced Security Erase Unit Completion
USHORT CurrentAdvancePowerMng; // 91 CurrentAdvanced Power Managemnt Value
USHORT MasterPasswordRevisionCode; // 92 Master Password Revision Code
USHORT HardwareResetResult; // 93 Hardware Reset Result
UCHAR CurrentAcousticManagement; // 94 Acoustic Management (low byte = current; high byte = vendor recommended)
UCHAR VendorAcousticManagement;
USHORT Reserved7a[99-95+1]; // 95-99
ULONG lMaxLBAAddress[2]; // 100-103 Maximum User LBA for 48-bit Address feature set
USHORT Reserved7b[126-104+1]; // 104-126
USHORT MediaStatusNotification:2; // 127 Removable Media Status Notification Support
USHORT SecurityStatus; // 128 Security Status
USHORT Reserved8[31]; // 129-159 Vendor Specific
USHORT CFAPowerMode1; // 160
USHORT Reserved9[94]; // 161-254
USHORT IntegrityWord; // 255 Checksum & Signature
} IDENTIFY_DATA, *PIDENTIFY_DATA;
#pragma pack()
//
// ATAPI typical command packet setup
//
typedef struct _ATAPI_COMMAND_PACKET {
UCHAR Opcode; // 00 ATAPI opcode
UCHAR Byte_1; // 01 reserved
UCHAR Byte_2; // 02 Starting LBA MSB
UCHAR Byte_3; // 03 LBA
UCHAR Byte_4; // 04 LBA
UCHAR Byte_5; // 05 LBA MSB
UCHAR Byte_6; // 06 X-FER length MSB
UCHAR Byte_7; // 07 X-FER length
UCHAR Byte_8; // 08 X-FER length or LSB if opcode is BEh
UCHAR Byte_9; // 09 X-FER length LSB / or FLAG bits
UCHAR Byte_10; // 10 MISC.
UCHAR Byte_11; // 11 reserved
UCHAR Byte_12; // 12 reserved
UCHAR Byte_13; // 13 reserved
UCHAR Byte_14; // 14 reserved
UCHAR Byte_15; // 15 reserved
HANDLE pIoReq; // Pointer to the corresponding Ioctl Request
} ATAPI_COMMAND_PACKET, *PATAPI_COMMAND_PACKET;
#define BEW_TO_W(x) ((x << 8) + (x >> 8))
#define W_TO_BEW(x) ((x << 8) + (x >> 8))
#define BEDW_TO_DW(x) ((x >> 24) + ((x & 0x00ff0000) >> 8) + ((x & 0x0000ff00) << 8) + ( x << 24))
#define DW_TO_BEDW(x) ((x >> 24) + ((x & 0x00ff0000) >> 8) + ((x & 0x0000ff00) << 8) + ( x << 24))
#define LBA_LSB(plba) (*((BYTE *)(((BYTE *)plba)) + 0))
#define LBA_2ndLSB(plba) (*((BYTE *)(((BYTE *)plba)) + 1))
#define LBA_3rdLSB(plba) (*((BYTE *)(((BYTE *)plba)) + 2))
#define LBA_4thLSB(plba) (*((BYTE *)(((BYTE *)plba)) + 3))
#define LBA_MSB(plba) LBA_4thLSB(plba)
//
// NOTE: I'm not sure where the following information was pulled from - perhaps
// an early ATA/PI document. According to revision 6:
// 00 = Device shall set DRQ to one within 3 ms of receiving PACKET command
// 01 = Obsolete
// 10 = Device shall set DRQ to one within 50 us of receiving PACKET command
// 11 = Reserved
//
#define ATA_DRQTYPE_INTRQ 1 // INTRQ will be asserted with DRQ within 10ms
#define ATA_DRQTYPE_ACCDRQ 2 // no INTRQ but DRQ will be asserted within 50 us of
// issuing ATAPI packet command (0xA0)
//
// ATAPI TOC data struct
// Data returned by the ATAPI_PACKET_CMD_READ_TOC command
//
typedef struct _ATAPI_TOC_DATA {
USHORT TOC_Data[0xFF];
} ATAPI_TOC_DATA, *PATAPI_TOC_DATA;
typedef struct _INQUIRY_DATA {
UCHAR inqDevType;
UCHAR inqRMB;
UCHAR inqVersion;
UCHAR inqAtapiVersion;
UCHAR inqLength;
UCHAR inqReserved[3];
UCHAR inqVendor[8];
UCHAR inqProdID[16];
UCHAR inqRev[4];
UCHAR inqReserved2[60];
} INQUIRY_DATA, *PINQUIRY_DATA;
#endif //_ATAPI_H_
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