📄 startup.s
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ldr r1, =PT_1ST_ENTRY_CNB ; Cache/Unbuffer/RW
str r1, [r0]
; uncached area.
add r0, r0, #0x0800 ; PTE entry for VA = 0x02000000
ldr r1, =PT_1ST_ENTRY_NCNB ; Uncache/Unbuffer/RW
str r1, [r0]
; Comment:
; The following loop is to direct map RAM VA == PA. i.e.
; VA == 0x50XXXXXX => PA == 0x50XXXXXX for S3C6410
; Fill in 8 entries to have a direct mapping for DRAM
ldr r10, =PT_1ST_BASE ; Restore address of 1st level page table
ldr r0, =DRAM_BASE_PA_START
add r10, r10, #PTR_1ST_PTE ; (r10) = ptr to 1st PTE for 0x50000000
add r0, r0, #0x1E ; 1MB cachable bufferable
orr r0, r0, #0x400 ; set kernel r/w permission
mov r1, #0
; mov r3, #64 ; 64MB DRAM
mov r3, #128 ; 128MB DRAM
45
mov r2, r1 ; (r2) = virtual address to map Bank at
cmp r2, #0x20000000:SHR:BANK_SHIFT
add r2, r10, r2, LSL #BANK_SHIFT-18
strlo r0, [r2]
add r0, r0, #0x00100000 ; (r0) = PTE for next physical page
subs r3, r3, #1
add r1, r1, #1
bgt %B45
ldr r10, =PT_1ST_BASE ; (r10) = restore address of 1st level page table
; The page tables and exception vectors are setup.
; Initialize the MMU and turn it on.
mov r1, #1
mcr p15, 0, r1, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r10, c2, c0, 0
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mrc p15, 0, r1, c1, c0, 0
orr r1, r1, #0x0071 ; Enable MMU
orr r1, r1, #0x0004 ; Enable the Data Cache
ldr r0, =VirtualStart
cmp r0, #0 ; make sure no stall on "mov pc,r0" below
mcr p15, 0, r1, c1, c0, 0
mov pc, r0 ; & jump to new virtual address
nop
; MMU & caches now enabled.
; (r10) = physcial address of 1st level page table
;-----------------------------------------------
; MMU Enabled and Virtual Address is Valid from here
;-----------------------------------------------
VirtualStart
;--------------------------------------------------
; Initialize Stack
; Stack size and location information is in "image_cfg.inc"
;--------------------------------------------------
mrs r0, cpsr
bic r0, r0, #Mode_MASK
orr r1, r0, #Mode_IRQ | NOINT
msr cpsr_cxsf, r1 ; IRQMode
ldr sp, =IRQStack_VA ; IRQStack
bic r0, r0, #Mode_MASK | NOINT
orr r1, r0, #Mode_SVC
msr cpsr_cxsf, r1 ; SVCMode
ldr sp, =SVCStack_VA ; SVCStack
;------------------------------------
; Jump to Main() "C" Routine
;------------------------------------
b main
b . ; Should no be here...
ENTRY_END
;------------------------------------------------------------------------------
; End of StartUp
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;
; Launch Function
;
; Launch OS Image from DRAM
;
;------------------------------------------------------------------------------
LEAF_ENTRY Launch
ldr r2, = PhysicalStart
ldr r3, =(DRAM_BASE_CA_START - DRAM_BASE_PA_START)
sub r2, r2, r3 ; Calculate Address Offset between Virtual and Physical
mov r1, #0
mcr p15, 0, r1, c7, c5, 0 ; Invalidate Entire Instruction Cache
mcr p15, 0, r1, c7, c14, 0 ; Clean and Invalidate Entire Data Cache
mrc p15, 0, r1, c1, c0, 0
bic r1, r1, #0x0005 ; Disable MMU and Data Cache
mcr p15, 0, r1, c1, c0, 0
nop
mov pc, r2 ; Jump to PStart
nop
; MMU & caches now disabled.
PhysicalStart
mov r1, #0
mcr p15, 0, r1, c8, c7, 0 ; Flush the TLB
mov pc, r0 ; Jump to program we are launching.
ENTRY_END
LEAF_ENTRY ChangeCLKDIV
[ {FALSE} ;CHANGE_PLL_CLKDIV_ON_EBOOT
;-----------------------------------------------
; Change Operation Mode to Sync Mode or Async Mode
;-----------------------------------------------
ldr r0, =OTHERS
ldr r1, [r0]
and r1, r1, #0x40
cmp r1, #0x40 ; OTHERS[6] = 0:AsyncModde 1:SyncMode
[ (SYNCMODE)
bne System_SetSyncMode
|
beq System_SetAsyncMode
]
;---------------------------------------
; Check PLL and CLKDIV
;---------------------------------------
ldr r3, =0x83FF3F07 ; Mask for APLL_CON/MPLL_CON
ldr r4, =0x80FF3F07 ; Mask for EPLL_CON0
ldr r5, =0x0000FFFF ; Mask for EPLL_CON1
ldr r6, =0x0003FF17 ; Mask for CLKDIV0
ldr r0, =APLL_CON ; Check APLL
ldr r1, [r0]
and r1, r1, r3
ldr r2, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL)) ; APLL_CON value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =MPLL_CON ; Check MPLL
ldr r1, [r0]
and r1, r1, r3
ldr r2, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL)) ; MPLL_CON value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =EPLL_CON0 ; Check EPLL_CON0
ldr r1, [r0]
and r1, r1, r4
ldr r2, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL)) ; EPLL_CON0 value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =EPLL_CON1 ; Check EPLL_CON1
ldr r1, [r0]
and r1, r1, r5
ldr r2, =EPLL_KVAL ; EPLL_CON1 value to configure
cmp r1, r2
bne PLL_NeedToConfigure
ldr r0, =CLK_DIV0 ; Check CLKDIV0
ldr r1, [r0]
and r1, r1, r6
ldr r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0)) ; CLKDIV0 value to configure
cmp r1, r2
bne CLKDIV_NeedToConfigure
b PLL_CLKDIV_AlreadyConfigured ; APLL/MPLL/EPLL and CLKDIV0 is already configured
;------------------------------------
; Prepare to Change PLL
;------------------------------------
PLL_NeedToConfigure
;------------------------------------
; Disable PLL Clock Out
;------------------------------------
ldr r0, =CLK_SRC
ldr r1, [r0]
bic r1, r1, #0x7 ; FIN out
str r1, [r0]
ldr r0, =CLK_DIV0
ldr r1, [r0]
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, = ((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0))
orr r1, r1, r2
str r1, [r0]
;------------------------------------
; Change PLL Value
;------------------------------------
ldr r1, =0x4B1 ; Lock Time : 0x4b1 (100us @Fin12MHz) for APLL/MPLL
ldr r2, =0xE13 ; Lock Time : 0xe13 (300us @Fin12MHz) for EPLL
ldr r0, =APLL_LOCK
str r1, [r0] ; APLL Lock Time
str r1, [r0, #0x4] ; MPLL Lock Time
str r2, [r0, #0x8] ; EPLL Lock Time
ldr r0, =APLL_CON
ldr r1, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL))
str r1, [r0]
ldr r0, =MPLL_CON
ldr r1, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL))
str r1, [r0]
ldr r0, =EPLL_CON1
ldr r1, =EPLL_KVAL
str r1, [r0]
ldr r0, =EPLL_CON0
ldr r1, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL))
str r1, [r0]
;------------------------------------
; Set System Clock Divider
;------------------------------------
CLKDIV_NeedToConfigure
ldr r0, =CLK_DIV0
ldr r1, [r0]
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0))
orr r1, r1, r2
str r1, [r0]
;------------------------------------
; Enable PLL Clock Out
;------------------------------------
ldr r0, =CLK_SRC
ldr r1, [r0]
orr r1, r1, #0x7 ; PLL Clockout
str r1, [r0] ; System will be waiting for PLL unlocked after this instruction
PLL_CLKDIV_AlreadyConfigured
] ; CHANGE_PLL_CLKDIV_ON_EBOOT
ENTRY_END
;------------------------------------------------------------------------------
; End of Launch
;------------------------------------------------------------------------------
END
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