usb.c

6410BSP3

        EdbgOutputDebugString("%x,", pt[i]);
    EdbgOutputDebugString("]\n");
}


//////////
// Function Name : OTGDEV_WrPktBulkInEp
// Function Desctiption : This function reads data from the buffer and writes the data on Bulk In EP FIFO.
// Input : buf, address of the data buffer to write on Bulk In EP FIFO
//            num, size of the data to write on Bulk In EP FIFO(byte count)
// Output : NONE
// Version :
void OTGDEV_WrPktBulkInEp(UINT8 *buf, int num)
{
    int i;
    volatile UINT32 Wr_Data=0;

    for(i=0;i<num;i+=4)
    {
        Wr_Data=((*(buf+3))<<24)|((*(buf+2))<<16)|((*(buf+1))<<8)|*buf;
        Outp32(bulkIn_EP_FIFO, Wr_Data);
        buf += 4;
    }
}

//////////
// Function Name : OTGDEV_RdPktBulkOutEp
// Function Desctiption : This function reads data from Bulk Out EP FIFO and writes the data on the buffer.
// Input : buf, address of the data buffer to write
//            num, size of the data to read from Bulk Out EP FIFO(byte count)
// Output : NONE
// Version :
void OTGDEV_RdPktBulkOutEp(UINT8 *buf, int num)
{
    int i;
    volatile UINT32 Rdata;

    for (i=0;i<num;i+=4)
    {
        //Rdata = Inp32(bulkOut_EP_FIFO);
        Inp32(bulkOut_EP_FIFO, Rdata);

        buf[i] = (UINT8)Rdata;
        buf[i+1] = (UINT8)(Rdata>>8);
        buf[i+2] = (UINT8)(Rdata>>16);
        buf[i+3] = (UINT8)(Rdata>>24);
    }

    // increase global down pointer for usb download function
    g_pDownPt += num;
}



//////////
// Function Name : OTGDEV_IsUsbOtgSetConfiguration
// Function Desctiption : This function checks if Set Configuration is received from the USB Host.
// Input : NONE
// Output : configuration result
// Version :
BOOL OTGDEV_IsUsbOtgSetConfiguration(void)
{
    if (oOtgDev.m_uIsUsbOtgSetConfiguration == 0)
        return false;
    else
        return true;
}

//////////
// Function Name : OTGDEV_SetOpMode
// Function Desctiption : This function sets CSRs related to the operation mode.
// Input : eMode, operation mode(cpu or dma)
// Output : NONE
// Version :
void OTGDEV_SetOpMode(USB_OPMODE eMode)
{
    oOtgDev.m_eOpMode = eMode;

    Outp32(GINTMSK, INT_RESUME|INT_OUT_EP|INT_IN_EP|INT_ENUMDONE|INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY); //gint unmask
    Outp32(GAHBCFG, MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK);

    OTGDEV_SetOutEpXferSize(EP_TYPE_BULK, 1, oOtgDev.m_uBulkOutEPMaxPktSize);
    OTGDEV_SetInEpXferSize(EP_TYPE_BULK, 1, 0);

    Outp32(bulkOut_DOEPCTL, 1<<31|1<<26|2<<18|1<<15|oOtgDev.m_uBulkOutEPMaxPktSize<<0);        //bulk out ep enable, clear nak, bulk, usb active, next ep3, max pkt
    Outp32(bulkIn_DIEPCTL, 0<<31|1<<26|2<<18|1<<15|oOtgDev.m_uBulkInEPMaxPktSize<<0);        //bulk in ep enable, clear nak, bulk, usb active, next ep1, max pkt
}

//////////
// Function Name : OTGDEV_VerifyChecksum
// Function Desctiption : This function calculates the checksum by summing all downloaded data
//                        and then compares the result with the checksum value which DNW sent.
// Input : NONE
// Output : NONE
// Version :
void OTGDEV_VerifyChecksum(void)
{
    UINT8* CalcCSPt;
    UINT16 dnCS;
    UINT16 checkSum;

    EdbgOutputDebugString("\nChecksum is being calculated....\n");

    // checksum calculation
    CalcCSPt = (UINT8*)oOtgDev.m_uDownloadAddress;
    checkSum = 0;
    while((UINT32)CalcCSPt < (oOtgDev.m_uDownloadAddress+(oOtgDev.m_uDownloadFileSize-8)))
        checkSum += *CalcCSPt++;

    // checkSum was calculated including dnCS. So, dnCS should be subtracted.
    checkSum=checkSum - *((unsigned char *)(oOtgDev.m_uDownloadAddress+oOtgDev.m_uDownloadFileSize-8-2))
        - *( (unsigned char *)(oOtgDev.m_uDownloadAddress+oOtgDev.m_uDownloadFileSize-8-1) );

    dnCS=*((unsigned char *)(oOtgDev.m_uDownloadAddress+oOtgDev.m_uDownloadFileSize-8-2))+
        (*( (unsigned char *)(oOtgDev.m_uDownloadAddress+oOtgDev.m_uDownloadFileSize-8-1) )<<8);

    if (checkSum ==dnCS)
    {
        EdbgOutputDebugString("Checksum O.K.\n\n");
    }
    else
    {
        EdbgOutputDebugString("Checksum Value => MEM:%x DNW:%x\n",checkSum,dnCS);
        EdbgOutputDebugString("Checksum failed.\n\n");
    }

}

BOOL InitializeUSB()
{
    OTGDEV_InitOtg(USB_HIGH);

    g_pDownPt = (UINT8 *)DMABUFFER;
    readPtIndex = DMABUFFER;

    return TRUE;
}

void InitializeInterrupt(void)
{
    s6410VIC0 = (S3C6410_VIC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_VIC0, FALSE);
    s6410VIC1 = (S3C6410_VIC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_VIC1, FALSE);

    System_DisableVIC();
    System_DisableIRQ();
    System_DisableFIQ();

    // Disable All Interrupts
    s6410VIC0->VICINTENCLEAR = 0xFFFFFFFF;
    s6410VIC1->VICINTENCLEAR = 0xFFFFFFFF;
    s6410VIC0->VICSOFTINTCLEAR = 0xFFFFFFFF;
    s6410VIC1->VICSOFTINTCLEAR = 0xFFFFFFFF;

    // All Interrupt is IRQ Mode
    s6410VIC0->VICINTSELECT = 0x0;
    s6410VIC1->VICINTSELECT = 0x0;

    // Clear Current Active Vector Address
    s6410VIC0->VICADDRESS = 0x0;
    s6410VIC1->VICADDRESS = 0x0;

    // Initialize Vector Table
    VIC_InitializeVectTable();

    EdbgOutputDebugString("INFO: (unsigned)C_IsrHandler : 0x%x\r\n", (unsigned)C_IsrHandler);
    EdbgOutputDebugString("INFO: (unsigned)ASM_IsrHandler : 0x%x\r\n", (unsigned)ASM_IsrHandler);

    // make value to assemble code "b IsrHandler"
    //EdbgOutputDebugString("INFO: (unsigned)pISR : 0x%x\r\n", (unsigned)pISR);
    pISR = (unsigned)(0xEA000000)+(((unsigned)ASM_IsrHandler -(DRAM_BASE_CA_START + 0x18 + 0x8))>>2);

    System_EnableIRQ();

    EdbgOutputDebugString("INFO: (unsigned)pISR : 0x%x\r\n", (unsigned)pISR);
//    EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%x\r\n", (unsigned)IsrHandler);

    VIC_InterruptEnable(PHYIRQ_OTG);
}

void C_IsrHandler(unsigned int val)
{
    UINT32 irq, irq2;

    irq = s6410VIC0->VICADDRESS;
    irq2 = s6410VIC1->VICADDRESS;

    if (irq == PHYIRQ_OTG)
    {
        VIC_InterruptDisable(PHYIRQ_OTG);
        OTGDEV_HandleEvent();
        VIC_InterruptEnable(PHYIRQ_OTG);
    }

    VIC_ClearVectAddr();
}

#pragma optimize ("",off)
BOOL UbootReadData(DWORD cbData, LPBYTE pbData)
{
    while(1)
    {
        if ( (DWORD)g_pDownPt >= readPtIndex + cbData )
        {
            memcpy((PVOID)pbData, (PVOID)readPtIndex, cbData);

            // Clear Partial Download Memory to 0xFF, Unless Gabage data will be written to Boot Media
            memset((PVOID)readPtIndex, 0xFF, cbData);

            readPtIndex += cbData;
            break;
        }
        else if((DWORD)g_pDownPt == DMABUFFER)
        {

        }
    }
    return TRUE;
}
#pragma optimize ("",on)

static void VIC_InterruptEnable(UINT32 intNum)
{
    if(intNum<32)
    {
        s6410VIC0->VICINTENABLE = (1<<intNum);
    }
    else
    {
        s6410VIC1->VICINTENABLE = (1<<(intNum-32));
    }

    return;
}

static void VIC_InterruptDisable(UINT32 intNum)
{
    if(intNum<32)
    {
        s6410VIC0->VICINTENCLEAR = (1<<intNum);
    }
    else
    {
        s6410VIC1->VICINTENCLEAR = (1<<(intNum-32));
    }

    return;
}

static void VIC_ClearVectAddr(void)
{
    s6410VIC0->VICADDRESS = 0x0;
    s6410VIC1->VICADDRESS = 0x0;

    return;
}

static void VIC_InitializeVectTable(void)
{
    s6410VIC0->VICVECTADDR0 = PHYIRQ_EINT0;
    s6410VIC0->VICVECTADDR1 = PHYIRQ_EINT1;
    s6410VIC0->VICVECTADDR2 = PHYIRQ_RTC_TIC;
    s6410VIC0->VICVECTADDR3 = PHYIRQ_CAMIF_C;
    s6410VIC0->VICVECTADDR4 = PHYIRQ_CAMIF_P;

    s6410VIC0->VICVECTADDR5 = PHYIRQ_I2C1;
    s6410VIC0->VICVECTADDR6 = PHYIRQ_I2S_V40;
    s6410VIC0->VICVECTADDR7 = PHYIRQ_SSS;
    s6410VIC0->VICVECTADDR8 = PHYIRQ_3D;

    s6410VIC0->VICVECTADDR9 = PHYIRQ_POST;
    s6410VIC0->VICVECTADDR10 = PHYIRQ_ROTATOR;
    s6410VIC0->VICVECTADDR11 = PHYIRQ_2D;
    s6410VIC0->VICVECTADDR12 = PHYIRQ_TVENC;
    s6410VIC0->VICVECTADDR13 = PHYIRQ_TVSCALER;
    s6410VIC0->VICVECTADDR14 = PHYIRQ_BATF;
    s6410VIC0->VICVECTADDR15 = PHYIRQ_JPEG;
    s6410VIC0->VICVECTADDR16 = PHYIRQ_MFC;
    s6410VIC0->VICVECTADDR17 = PHYIRQ_SDMA0;
    s6410VIC0->VICVECTADDR18 = PHYIRQ_SDMA1;
    s6410VIC0->VICVECTADDR19 = PHYIRQ_ARM_DMAERR;
    s6410VIC0->VICVECTADDR20 = PHYIRQ_ARM_DMA;
    s6410VIC0->VICVECTADDR21 = PHYIRQ_ARM_DMAS;
    s6410VIC0->VICVECTADDR22 = PHYIRQ_KEYPAD;
    s6410VIC0->VICVECTADDR23 = PHYIRQ_TIMER0;
    s6410VIC0->VICVECTADDR24 = PHYIRQ_TIMER1;
    s6410VIC0->VICVECTADDR25 = PHYIRQ_TIMER2;
    s6410VIC0->VICVECTADDR26 = PHYIRQ_WDT;
    s6410VIC0->VICVECTADDR27 = PHYIRQ_TIMER3;
    s6410VIC0->VICVECTADDR28 = PHYIRQ_TIMER4;
    s6410VIC0->VICVECTADDR29 = PHYIRQ_LCD0_FIFO;
    s6410VIC0->VICVECTADDR30 = PHYIRQ_LCD1_FRAME;
    s6410VIC0->VICVECTADDR31 = PHYIRQ_LCD2_SYSIF;

    s6410VIC1->VICVECTADDR0 = PHYIRQ_EINT2;
    s6410VIC1->VICVECTADDR1 = PHYIRQ_EINT3;
    s6410VIC1->VICVECTADDR2 = PHYIRQ_PCM0;
    s6410VIC1->VICVECTADDR3 = PHYIRQ_PCM1;
    s6410VIC1->VICVECTADDR4 = PHYIRQ_AC97;
    s6410VIC1->VICVECTADDR5 = PHYIRQ_UART0;
    s6410VIC1->VICVECTADDR6 = PHYIRQ_UART1;
    s6410VIC1->VICVECTADDR7 = PHYIRQ_UART2;
    s6410VIC1->VICVECTADDR8 = PHYIRQ_UART3;
    s6410VIC1->VICVECTADDR9 = PHYIRQ_DMA0;
    s6410VIC1->VICVECTADDR10 = PHYIRQ_DMA1;
    s6410VIC1->VICVECTADDR11 = PHYIRQ_ONENAND0;
    s6410VIC1->VICVECTADDR12 = PHYIRQ_ONENAND1;
    s6410VIC1->VICVECTADDR13 = PHYIRQ_NFC;
    s6410VIC1->VICVECTADDR14 = PHYIRQ_CFC;
    s6410VIC1->VICVECTADDR15 = PHYIRQ_UHOST;
    s6410VIC1->VICVECTADDR16 = PHYIRQ_SPI0;
    s6410VIC1->VICVECTADDR17 = PHYIRQ_SPI1;
    s6410VIC1->VICVECTADDR18 = PHYIRQ_I2C;
    s6410VIC1->VICVECTADDR19 = PHYIRQ_HSITX;
    s6410VIC1->VICVECTADDR20 = PHYIRQ_HSIRX;
    s6410VIC1->VICVECTADDR21 = PHYIRQ_RESERVED;
    s6410VIC1->VICVECTADDR22 = PHYIRQ_MSM;
    s6410VIC1->VICVECTADDR23 = PHYIRQ_HOSTIF;
    s6410VIC1->VICVECTADDR24 = PHYIRQ_HSMMC0;
    s6410VIC1->VICVECTADDR25 = PHYIRQ_HSMMC1;
    s6410VIC1->VICVECTADDR26 = PHYIRQ_OTG;
    s6410VIC1->VICVECTADDR27 = PHYIRQ_IRDA;
    s6410VIC1->VICVECTADDR28 = PHYIRQ_RTC_ALARM;
    s6410VIC1->VICVECTADDR29 = PHYIRQ_SEC;
    s6410VIC1->VICVECTADDR30 = PHYIRQ_PENDN;
    s6410VIC1->VICVECTADDR31 = PHYIRQ_ADC;
}

static void delayLoop(int count)
{
    volatile int j,i;
    for(j = 0; j < count; j++)
        for(i=0;i<1000;i++);
}