startup.s

6410BSP3

        ldr        r0, =DRAM_BASE_PA_START    ; DRAM Base Physical Address
        add        r0, r0, #IMAGE_NK_OFFSET        ; NK Offset in DRAM
        mov        pc, r0                        ; Jump to StartUp address
        b        .

Normal_Boot_Sequence
;------------------------------------
;	Power Management Routine
;	(Software Reset Processing)
;------------------------------------
		ldr		r0, =RST_STAT
		ldr		r1, [r0]
    [   (CPU_REVISION = EVT0)
		tst		r1, #(1<<5)             ; SW_RST
    |
		tst		r1, #(1<<2)             ; WDT_RST
    ]
		beq		BringUpWinCE                     ; if not booted up from SW_RST, Skip

		ldr		r0, =DRAM_BASE_PA_START	; DRAM Base Physical Address
		add		r0, r0, #IMAGE_NK_OFFSET		; NK Offset in DRAM
		mov		pc, r0						; Jump to StartUp address
		b		.

BringUpWinCE
;------------------------------------
;    Clear DRAM
;------------------------------------

    [ {TRUE}
        mov        r1, #0
        mov     r2, #0
        mov     r3, #0
        mov     r4, #0
        mov     r5, #0
        mov     r6, #0
        mov     r7, #0
        mov     r8, #0

        ldr        r0, =DRAM_BASE_PA_START    ; Start address (Physical 0x5000.0000)
        ldr        r9, =DRAM_SIZE                ; 128 MB of RAM
10
        stmia    r0!, {r1-r8}
        subs        r9, r9, #32
        bne        %B10
    ]

;------------------------------------
;    Jump to Main() "C" Routine
;------------------------------------

        LED_ON 0x8

        bl        main
        b         .            ; Should not be here...

        ENTRY_END

;-----------------------------------------------------------------------------
;
;    CPU MODE Setting
;
;    SyncMode or AsyncMode
;
;-----------------------------------------------------------------------------
    ;---------------------------
    ;    Set to Synchronous Mode
    ;---------------------------
    LEAF_ENTRY System_SetSyncMode

        ldr        r0, =OTHERS
        ldr        r1, [r0]
        orr        r1, r1, #0x40            ; SyncMUXSEL = DOUT_APLL
        str        r1, [r0]

        nop
        nop
        nop
        nop
        nop

        ldr        r1, [r0]
        orr        r1, r1, #0x80            ; SyncReq = request Sync
        str        r1, [r0]

WaitForSync
        ldr        r1, [r0]                ; Read OTHERS
        and        r1, r1, #0xF00            ; Wait SYNCMODEACK = 0xF
        cmp        r1, #0xF00
        bne        WaitForSync

        mov        pc, lr

        ENTRY_END


    ;---------------------------
    ;    Set to Asynchronous Mode
    ;---------------------------
    LEAF_ENTRY System_SetAsyncMode

        ldr        r0, =OTHERS
        ldr        r1, [r0]
        bic        r1, r1, #0xC0
        orr        r1, r1, #0x40            ; SyncReq = Async, SyncMUX = Sync
        str        r1, [r0]

WaitForAsync
        ldr        r1, [r0]                ; Read OTHERS
        and        r1, r1, #0xF00            ; Wait SYNCMODEACK = 0x0
        cmp        r1, #0x0
        bne        WaitForAsync

        ldr        r0, =OTHERS
        ldr        r1, [r0]
        bic        r1, r1, #0x40            ; SyncMUX = Async
        str        r1, [r0]

        nop
        nop
        nop
        nop
        nop

        mov        pc, lr

        ENTRY_END



;------------------------------------------------------------------------------
;
;    InitDMC Function
;
;    Initialize DMC(Dynamic Memory Controller) and DRAM
;
;------------------------------------------------------------------------------

    LEAF_ENTRY InitDMC

;---------------------------
; Initialize DMC (mDDR)
;---------------------------

    [    USE_DMC1

        ldr        r0, =DMC1_BASE                    ; DMC1 base address

        ldr        r1, =0x4
        str        r1, [r0, #INDEX_MEMCCMD]            ; Enter the Config. Mode

        ldr        r1, =DMC_DDR_REFRESH_PRD        ; Timing Para.
        str        r1, [r0, #INDEX_REFRESH]

        ldr        r1, =DMC_DDR_CAS_LATENCY
        str        r1, [r0, #INDEX_CASLAT]

        ldr        r1, =DMC_DDR_t_DQSS
        str        r1, [r0, #INDEX_T_DQSS]

        ldr        r1, =DMC_DDR_t_MRD
        str        r1, [r0, #INDEX_T_MRD]

        ldr        r1, =DMC_DDR_t_RAS
        str        r1, [r0, #INDEX_T_RAS]

        ldr        r1, =DMC_DDR_t_RC
        str        r1, [r0, #INDEX_T_RC]

        ldr        r1, =DMC_DDR_t_RCD
        ldr        r2, =DMC_DDR_schedule_RCD
        orr        r1, r1, r2
        str        r1, [r0, #INDEX_T_RCD]

        ldr        r1, =DMC_DDR_t_RFC
        ldr        r2, =DMC_DDR_schedule_RFC
        orr        r1, r1, r2
        str        r1, [r0, #INDEX_T_RFC]

        ldr        r1, =DMC_DDR_t_RP
        ldr        r2, =DMC_DDR_schedule_RP
        orr        r1, r1, r2
        str        r1, [r0, #INDEX_T_RP]

        ldr        r1, =DMC_DDR_t_RRD
        str        r1, [r0, #INDEX_T_RRD]

        ldr        r1, =DMC_DDR_t_WR
        str        r1, [r0, #INDEX_T_WR]

        ldr        r1, =DMC_DDR_t_WTR
        str        r1, [r0, #INDEX_T_WTR]

        ldr        r1, =DMC_DDR_t_XP
        str        r1, [r0, #INDEX_T_XP]

        ldr        r1, =DMC_DDR_t_XSR
        str        r1, [r0, #INDEX_T_XSR]

        ldr        r1, =DMC_DDR_t_ESR
        str        r1, [r0, #INDEX_T_ESR]

        ldr        r1, =DMC1_MEM_CFG
        str        r1, [r0, #INDEX_MEMCFG]

        ldr        r1, =DMC1_MEM_CFG2
        str        r1, [r0, #INDEX_MEMCFG2]

    [    USE_DMC1_CHIP0
        ldr        r1, =DMC1_CHIP0_CFG
        str        r1, [r0, #INDEX_CHIP0_CFG]
    ]

    [    USE_DMC1_CHIP1
        ldr        r1, =DMC1_CHIP1_CFG
        str        r1, [r0, #INDEX_CHIP1_CFG]
    ]

        ldr        r1, =DMC1_USER_CFG
        str        r1, [r0, #INDEX_USER_CFG]

    ;---------------------------------------------
    ; DMC1 DDR Chip 0 configuration direct command reg
    ;---------------------------------------------
    [    USE_DMC1_CHIP0

        ; DMC1 DDR Chip 0 configuration direct command reg
        ; NOP
        ldr        r1, =DMC_NOP0
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; Precharge All
        ldr        r1, =DMC_PA0
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; Auto Refresh    2 time
        ldr        r1, =DMC_AR0
        str        r1, [r0, #INDEX_DIRECTCMD]
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; EMRS
        ldr        r1, =DMC_mDDR_EMR0            ; DS:Full, PASR:Full Array
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; Mode Reg (MRS, CAS3, BL4)
        ldr        r1, =DMC_mDDR_MR0
        str        r1, [r0, #INDEX_DIRECTCMD]

    ] ; USE_DMC1_CHIP0

    ;---------------------------------------------
    ; DMC1 DDR Chip 1 configuration direct command reg
    ;---------------------------------------------
    [    USE_DMC1_CHIP1

        ; DMC1 DDR Chip 1 configuration direct command reg
        ; NOP
        ldr        r1, =DMC_NOP1
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; Precharge All
        ldr        r1, =DMC_PA1
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; Auto Refresh    2 time
        ldr        r1, =DMC_AR1
        str        r1, [r0, #INDEX_DIRECTCMD]
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; EMRS
        ldr        r1, =DMC_mSDR_EMR1            ; DS:Full, PASR:Full Array
        str        r1, [r0, #INDEX_DIRECTCMD]

        ; Mode Reg (MRS, CAS3, BL4)
        ldr        r1, =DMC_mDDR_MR1
        str        r1, [r0, #INDEX_DIRECTCMD]

    ] ; USE_DMC1_CHIP1

        ; Enable DMC1
        mov        r1, #0x0
        str        r1, [r0, #INDEX_MEMCCMD]

Wait_for_DMC1Ready

        ldr        r1, [r0, #INDEX_MEMSTAT]
        mov        r2, #0x3
        and        r1, r1, r2
        cmp        r1, #0x1
        bne        Wait_for_DMC1Ready

    ] ; USE_DMC1

        NOP

        mov     pc, lr

        ENTRY_END

        END