📄 startup.s
字号:
ldr r1, =0x4B1 ; Lock Time : 0x4b1 (100us @Fin12MHz) for APLL/MPLL
ldr r2, =0xE13 ; Lock Time : 0xe13 (300us @Fin12MHz) for EPLL
ldr r0, =APLL_LOCK
str r1, [r0] ; APLL Lock Time
str r1, [r0, #0x4] ; MPLL Lock Time
str r2, [r0, #0x8] ; EPLL Lock Time
ldr r0, =APLL_CON
ldr r1, =((1<<31)+(APLL_MVAL<<16)+(APLL_PVAL<<8)+(APLL_SVAL))
str r1, [r0]
ldr r0, =MPLL_CON
ldr r1, =((1<<31)+(MPLL_MVAL<<16)+(MPLL_PVAL<<8)+(MPLL_SVAL))
str r1, [r0]
ldr r0, =EPLL_CON1
ldr r1, =EPLL_KVAL
str r1, [r0]
ldr r0, =EPLL_CON0
ldr r1, =((1<<31)+(EPLL_MVAL<<16)+(EPLL_PVAL<<8)+(EPLL_SVAL))
str r1, [r0]
;------------------------------------
; Set System Clock Divider
;------------------------------------
CLKDIV_NeedToConfigure
ldr r0, =CLK_DIV0
ldr r1, [r0]
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =((PCLK_DIV<<12)+(HCLKx2_DIV<<9)+(HCLK_DIV<<8)+(MPLL_DIV<<4)+(APLL_DIV<<0)) ; CLKDIV0 value to configure
orr r1, r1, r2
str r1, [r0]
;------------------------------------
; Enable PLL Clock Out
;------------------------------------
ldr r0, =CLK_SRC
ldr r1, [r0]
orr r1, r1, #0x7 ; PLL Clockout
str r1, [r0] ; System will be waiting for PLL unlocked after this instruction
PLL_CLKDIV_AlreadyConfigured
] ; CHANGE_PLL_CLKDIV_ON_KERNEL
;------------------------------------
; Expand Memory Port 1 to x32
;------------------------------------
ldr r0, =MEM_SYS_CFG
ldr r1, [r0]
bic r1, r1, #0x80 ; ADDR_EXPAND to "0"
str r1, [r0]
;------------------------------------
; Store BSP Data
;------------------------------------
ldr r0, =INFORM0
ldr r1, =0x64107618 ; June 18, 2007
str r1, [r0]
;------------------------------------
; Enable VFP via Coprocessor Access Cotrol Register
;------------------------------------
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00F00000
mcr p15, 0, r0, c1, c0, 2
;------------------------------------
; Add following: SISO added
; Enable FPEXC enable bit to enable VFP
;------------------------------------
MOV r1, #0
MCR p15, 0, r1, c7, c5, 4
MOV r0,#VFPEnable
FMXR FPEXC, r0 ; FPEXC = r0
nop
nop
nop
nop
nop
;------------------------------------
; Power Management Routine
; (WakeUp Processing)
;------------------------------------
[ {TRUE}
ldr r0, =RST_STAT
ldr r1, [r0]
and r1, r1, #0x3F
cmp r1, #0x8
bne BringUp_WinCE_from_Reset ; Normal Mode Booting
LED_ON 0xC
;-------------------------------
; Calculate CheckSum of Sleep Data
ldr r3, =IMAGE_SLEEP_DATA_PA_START ; Base of Sleep Data Area
ldr r2, =0x0 ; CheckSum is in r2
ldr r0, =(SLEEPDATA_SIZE-1) ; Size of Sleep Data Area (in words)
ReCheckSum_Loop
ldr r1, [r3], #4
and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1 ; CheckSum is in r2
subs r0, r0, #1
bne ReCheckSum_Loop
ldr r0, =INFORM1
ldr r1, [r0]
cmp r1, r2 ; Compare CheckSum Recalculated and Value in DRAM
bne CheckSum_Corrupted
CheckSum_Granted
;-------------------------------
; Restore CP15 Register
ldr r10, =IMAGE_SLEEP_DATA_PA_START ; Base of Sleep Data Area
ldr r6, [r10, #SleepState_MMUDOMAIN] ; Domain Access Control Register
ldr r5, [r10, #SleepState_MMUTTBCTL] ; TTB Control Register
ldr r4, [r10, #SleepState_MMUTTB1] ; TTB Register1
ldr r3, [r10, #SleepState_MMUTTB0] ; TTB Register0
ldr r2, [r10, #SleepState_SYSCTL] ; System Control Register
ldr r1, [r10, #SleepState_WakeAddr] ; Return Address
nop
nop
nop
nop
nop
mcr p15, 0, r6, c3, c0, 0 ; Restore Domain Access Control Register
mcr p15, 0, r5, c2, c0, 2 ; Restore TTB Control Register
mcr p15, 0, r4, c2, c0, 1 ; Restore TTB Register1
mcr p15, 0, r3, c2, c0, 0 ; Restore TTB Register0
mov r0, #0x0
mcr p15, 0, r0, c8, c7, 0 ; Invalidate I & D TLB
mcr p15, 0, r2, c1, c0, 0 ; Restore System Control Register (MMU Control)
nop
nop
nop
nop
nop
;-------------------------------
; Return to WakeUp_Address
mov pc, r1 ; Jump to Virtual Return Address
b .
CheckSum_Corrupted
;--------------------------------
; Bad News... CheckSum is Corrupted
ldr r0, =DRAM_BASE_PA_START ; DRAM Base Physical Address
add r0, r0, #IMAGE_NK_OFFSET ; NK Offset in DRAM
mov pc, r0 ; Jump to StartUp address
]
;------------------------------------
; End of Power Management Routine
;------------------------------------
BringUp_WinCE_from_Reset
;------------------------------------
; Clear DRAM
;------------------------------------
[ CLEAR_DRAM_ON_KERNEL
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
ldr r0, =IMAGE_NK_PA_START ; Start address (physical 0x5200.0000)
ldr r9, =IMAGE_NK_SIZE ; 80 MB of RAM (1MB + 31MB + 80MB + 16MB)
10
stmia r0!, {r1-r8}
subs r9, r9, #32
bne %B10
]
;------------------------------------
; Flush TLB, Invalidate ICache, DCache
;------------------------------------
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 ; flush both TLB
mcr p15, 0, r0, c7, c5, 0 ; invalidate instruction cache
mcr p15, 0, r0, c7, c6, 0 ; invalidate data cache
;------------------------------------
; Disable VIC
;------------------------------------
bl System_DisableVIC
;------------------------------------
; Enable Branch Prediction
;------------------------------------
bl System_EnableBP
;------------------------------------
; MMU Option (for ARM1176, Just for Test)
;------------------------------------
[ {FALSE}
; Set MMU options
mrc p15, 0, r0, c1, c0, 0
;bic r0, r0, #(1 :SHL: 23) ; Clear the XP bit to enable subpage AP bit
;bic r0, r0, #(1 :SHL: 15) ; Clear the L4 bit to enable arm V6
;orr r0, r0, #(1 :SHL: 1) ; Set the A bit to enable alignment checking.
orr r0, r0, #(1 :SHL: 22) ; Set the U bit to enable unaligned access
;orr r0, r0, #(1 :SHL: 3) ; Write buffer wnable
mcr p15, 0, r0, c1, c0, 0
]
;------------------------------------
; Jump to KernelStart
;------------------------------------
add r0, pc, #g_oalAddressTable - (. + 8)
bl KernelStart
b . ; Should not be here...
ENTRY_END
;------------------------------------------------------------------------------
; End of ResetHandler
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; Place OemAddressTable here, This area is Text area
;------------------------------------------------------------------------------
INCLUDE oemaddrtab_cfg.inc
;------------------------------------------------------------------------------
;
; OALCPUPowerOff Function
;
; S3C6410 Sleep mode entering function
;
;------------------------------------------------------------------------------
LEAF_ENTRY OALCPUPowerOff
;------------------------------------
; 1. Push SVC Register into our Stack
;------------------------------------
stmdb sp!, {r4-r12}
stmdb sp!, {lr}
;------------------------------------------------
; 2. Save CP15 Register into Sleep Data Area in DRAM
;------------------------------------------------
ldr r3, =IMAGE_SLEEP_DATA_UA_START ; Sleep Data Area Base Address
;----------------------
; WakeUp Routine Address
ldr r2, =WakeUp_Address ; Virtual Address of WakeUp Routine
str r2, [r3], #4 ; [SleepState_WakeAddr]
;--------------------------
; CP15 System Control Register
mrc p15, 0, r2, c1, c0, 0 ; load r2 with System Control Register
ldr r0, =SYSCTL_SBZ_MASK ; Should Be Zero Mask for System Control Register
bic r2, r2, r0
ldr r0, =SYSCTL_SBO_MASK ; Should Be One Mask for System Control Register
orr r2, r2, r0
str r2, [r3], #4 ; [SleepState_SYSCTL]
;---------------------------------
; CP15 Translation Table Base Register0
mrc p15, 0, r2, c2, c0, 0 ; load r2 with TTB Register0
ldr r0, =MMUTTB_SBZ_MASK ; Should Be Zero Mask for TTB Register0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -