s3c6410_fil.h

6410BSP3

										if (DEV_ADDR_CYCLE > 4)			\
											NF_ADDR((nPpn>>16)&0xFF);	\
									}
#define NF_SET_CLK(tacls, twrph0, twrph1)		(pNANDFConReg->NFCONF = (pNANDFConReg->NFCONF&~0x7770)		\
											|NF_TACLS(tacls) | NF_TWRPH0(twrph0) | NF_TWRPH1(twrph1))

#define NF_WAIT_ECC_READY()	{	\
									while(!(pNANDFConReg->NF8ECCERR0&(1<<30)));	\
								}

#define NF_SETREG_8BITECC() {   \
                        		pNANDFConReg->NFCONF &= ~NF_MASK_ECC_BIT_INDICATES; \
                        		pNANDFConReg->NFCONF |= NF_8BIT_ECC;                \
                        		pNANDFConReg->NFCONT |= NF_8BIT_ECC_STOP_BIT;       \
                            }

#define NF_SETREG_4BITECC() {   \
                        		pNANDFConReg->NFCONF &= ~NF_MASK_ECC_BIT_INDICATES; \
                        		pNANDFConReg->NFCONF |= NF_4BIT_ECC;                \
                            }

///////////////////////////////////////////////
// NAND Flash Command Set
///////////////////////////////////////////////
#define CMD_READ_ID							(0x90)
#define CMD_READ								(0x00)
#define CMD_READ_CONFIRM						(0x30)
#define CMD_RESET								(0xFF)
#define CMD_PROGRAM							(0x80)
#define CMD_PROGRAM_CONFIRM					(0x10)
#define CMD_ERASE								(0x60)
#define CMD_ERASE_CONFIRM						(0xD0)
#define CMD_RANDOM_DATA_INPUT				(0x85)
#define CMD_RANDOM_DATA_OUTPUT				(0x05)
#define CMD_RANDOM_DATA_OUTPUT_CONFIRM		(0xE0)
#define CMD_READ_STATUS						(0x70)
#define CMD_READ_STATUS_CHIP0					(0xF1)
#define CMD_READ_STATUS_CHIP1					(0xF2)

// 2 Plane Program Sequence : 80h - 11h - 81h - 10h (Write CMD - 2Plane Dummy - 2 Plane Prog - Write Confirm)
#define CMD_2PLANE_PROGRAM					(0x81)
#define CMD_2PLANE_PROGRAM_DUMMY			(0x11)

// What is this CMD???
#define CMD_READ_FOR_COPY_BACK				(0x35)

#define NAND_STATUS_READY						(0x40)
#define NAND_STATUS_ERROR						(0x01)
#define NAND_STATUS_PLANE0_ERROR			(0x02)
#define NAND_STATUS_PLANE1_ERROR			(0x04)

///////////////////////////////////////////////
// NAND configuration definitions
///////////////////////////////////////////////
#define NAND_SPAREPAGE_SIZE			(256) // for supporting 8Bit-ECC 080926 hsjang

///////////////////////////////////////////////
// Main Area Layout (512 bytes x 4)
///////////////////////////////////////////////
// +----------+----------+----------+----------+
// | 512B     | 512B     | 512B     | 512B     |
// | Sector 0 | Sector 1 | Sector 2 | Sector 3 |
// +----------+----------+----------+----------+

///////////////////////////////////////////////
// Main Area Layout (512 bytes x 8) : 4KBytes/Page
///////////////////////////////////////////////
// +----------+----------+----------+----------+----------+----------+----------+----------+
// | 512B     | 512B     | 512B     | 512B     | 512B     | 512B     | 512B     | 512B     |
// | Sector 0 | Sector 1 | Sector 2 | Sector 3 | Sector 4 | Sector 5 | Sector 6 | Sector 7 |
// +----------+----------+----------+----------+----------+----------+----------+----------+
#define NAND_SECTOR_SIZE				(512)

///////////////////////////////////////////////
// Spare Area Layout (64 bytes) for 2KByte/Page
///////////////////////////////////////////////
// +-----+-------+----------+--------------+----------+----------+----------+----------+-----------+-----------+
// | 1B  | 1B    | 2B       | 12B          | 8B       | 8B       | 8B       | 8B       | 8B        | 8B (copy) |
// | Bad | Clean | Reserved | SpareContext | Sec0 ECC | Sec1 ECC | Sec2 ECC | Sec3 ECC | Spare ECC | Spare ECC |
// +-----+-------+----------+--------------+----------+----------+----------+----------+-----------+-----------+

///////////////////////////////////////////////
// Spare Area Layout (64 bytes) for 4KByte/Page
///////////////////////////////////////////////
// +-----+-------+----------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+-----------+
// | 1B  | 1B    | 2B       | 20B          | 8B       | 8B       | 8B       | 8B       | 8B       | 8B       | 8B       | 8B       | 8B        | 8B (copy) |
// | Bad | Clean | Reserved | SpareContext | Sec0 ECC | Sec1 ECC | Sec2 ECC | Sec3 ECC | Sec4 ECC | Sec5 ECC | Sec6 ECC | Sec7 ECC | Spare ECC | Spare ECC |
// +-----+-------+----------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+-----------+

///////////////////////////////////////////////
// Spare Area Layout (128 bytes) for 4KByte/Page : Read_Spare_Separate ( Total 120 Bytes are used )
///////////////////////////////////////////////
// +-----+-------+----------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+------------------+--------------------+
// | 1B  | 1B    | 2B       | 20B          | 8B       | 8B       | 8B       | 8B       | 8B       | 8B       | 8B       | 8B       | 16B (8bit ECC)   | 16B (8bit ECC)     |
// | Bad | Clean | Reserved | SpareContext | Sec0 ECC | Sec1 ECC | Sec2 ECC | Sec3 ECC | Sec4 ECC | Sec5 ECC | Sec6 ECC | Sec7 ECC | SpareContext ECC | ECC of Sec0 ~ Sec7 |
// +-----+-------+----------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+------------------+--------------------+

///////////////////////////////////////////////
// Spare Area Layout (218 bytes) for 4KByte/Page : Read_Spare_8BitECC ( Total 184 Bytes are used )
///////////////////////////////////////////////
// +-----+-------+----------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+-----------+
// | 1B  | 1B    | 2B       | 20B          | 16B      | 16B      | 16B      | 16B      | 16B      | 16B      | 16B      | 16B      | 16B       | 16B(copy) |
// | Bad | Clean | Reserved | SpareContext | Sec0 ECC | Sec1 ECC | Sec2 ECC | Sec3 ECC | Sec4 ECC | Sec5 ECC | Sec6 ECC | Sec7 ECC | Spare ECC | Spare ECC |
// +-----+-------+----------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-----------+-----------+

///////////////////////////////////////////////
// ECC Spare context definitions
///////////////////////////////////////////////
#define NAND_SCXT_OFFSET	(4)		// 1B+1B+2B
#define NAND_MECC_OFFSET	(16)		// 1B+1B+2B+12B
#define NAND_SECC_OFFSET	(48)		// 1B+1B+2B+12B+32B
#define NAND_SECC2_OFFSET	(56)		// 1B+1B+2B+12B+32B+8B
// for 4KByte/Page
#define NAND_MECC_OFFSET_4K	(24)		// 1B+1B+2B+20B
#define NAND_SECC_OFFSET_4K	(88)		// 1B+1B+2B+20B+64B
#define NAND_SECC_OFFSET_8BIT_ECC_4K	(152)		// 1B+1B+2B+20B+128B
#define NAND_SECC2_OFFSET_4K	(96)		// 1B+1B+2B+20B+64B+8B
#define NAND_SECC2_OFFSET_8BIT_ECC_4K	(168)		// 1B+1B+2B+20B+128B+16B

typedef struct {
	UINT8	cBadMark;			// 1 bytes bad mark
	UINT8	cCleanMark;			// 1 Byte clean mark
	UINT8	cReserved[2];		// 2 byte Reserved
	INT32	aSpareData[5];		// 20 bytes spare data, use only 12 byte for 2KByte/Page
	UINT32	aMECC[8*4];			// 32 bytes ECC for Sec0~Sec3 in Main Area, 
	                            // 64 bytes ECC for Sec4~Sec7 in Main Area for 4K page, 
	                            // 128 byte for sec0~7 8Bit ECC data
	UINT32	aSECC[8];			// 8 bytes ECC x 2 for Spare Area
} SECCCxt, *pSECCCxt;

// Default NAND Flash timing @HCLK 133MHz (tHCLK = 7.5ns)
//#define	 DEFAULT_TACLS		(1)	// 1 HCLK (7.5ns)
//#define	 DEFAULT_TWRPH0	(4)	// 5 HCLK (37.5ns)
//#define	 DEFAULT_TWRPH1	(1)	// 2 HCLK (15ns)

#define	 DEFAULT_TACLS	(1)//(1)	// 1 HCLK (7.5ns) 777
#define	 DEFAULT_TWRPH0	(6)//(4)	// 5 HCLK (37.5ns)
#define	 DEFAULT_TWRPH1	(1)//(1)	// 2 HCLK (15ns)
#define	 MAX_RW_TACLS	(7)
#define	 MAX_RW_TWRPH0	(7)
#define	 MAX_RW_TWRPH1	(7)

// for ECC decoding with Dummy Data
#define	 DUMMY_R_TACLS	(0)
#define	 DUMMY_R_TWRPH0	(1)
#define	 DUMMY_R_TWRPH1	(1)

// for ECC encoding with Dummy Data
#define	 DUMMY_W_TACLS	(0)
#define	 DUMMY_W_TWRPH0	(0)
#define	 DUMMY_W_TWRPH1	(0)

///////////////////////////////////////////////
// Exported Function Prototype of FIL
///////////////////////////////////////////////

#ifdef __cplusplus
	extern "C" {
#endif

INT32 NAND_Init(VOID);
VOID  NAND_Reset (UINT32 nBank);
INT32 NAND_Read(UINT32 nBank, UINT32 nPpn, UINT32 nSctBitmap, UINT32 nPlaneBitmap,
				UINT8* pDBuf, UINT8* pSBuf, BOOL32 bECCIn, BOOL32 bCleanCheck);
INT32 NAND_Read_Retry(UINT32 nBank, UINT32 nPpn, UINT32 nSctBitmap, UINT32 nPlaneBitmap,
				UINT8* pDBuf, UINT8* pSBuf, BOOL32 bECCIn, BOOL32 bCleanCheck);
VOID NAND_Write(UINT32 nBank, UINT32 nPpn, UINT32 nSctBitmap,
				UINT32 nPlaneBitmap, UINT8* pDBuf, UINT8* pSBuf);
VOID NAND_Write_AfterCheck(UINT32 nBank, UINT32 nPpn, UINT32 nSctBitmap,
				UINT32 nPlaneBitmap, UINT8* pDBuf, UINT8* pSBuf);
VOID  NAND_Erase (UINT32 nBank, UINT32 nPbn, UINT32 nPlaneBitmap);
INT32 NAND_Sync (UINT32 nBank, UINT32 *nPlaneBitmap);
VOID NAND_Steploader_Write(UINT32 nBank, UINT32 nPpn, UINT32 nSctBitmap,
				UINT32 nPlaneBitmap, UINT8* pDBuf, UINT8* pSBuf);
VOID NAND_GetPlatformInfo(FILPlatformInfo* pstFILPlatformInfo);
#ifdef __cplusplus
}
#endif

#endif	// __S3C6410_FIL_H__