s3c6410_fil.h

6410BSP3

///////////////////////////////////////////////////////////////
//
//	MODULE		: FIL
//	NAME		: S3C6410X Flash Interface Layer
//	FILE			: S3C6410X_NAND.h
//	PURPOSE		:
//
///////////////////////////////////////////////////////////////
//
//		COPYRIGHT 2003-2006 SAMSUNG ELECTRONICS CO., LTD.
//					ALL RIGHTS RESERVED
//
//	Permission is hereby granted to licensees of Samsung Electronics
//	Co., Ltd. products to use or abstract this computer program for the
//	sole purpose of implementing a product based on Samsung
//	Electronics Co., Ltd. products. No other rights to reproduce, use,
//	or disseminate this computer program, whether in part or in whole,
//	are granted.
//
//	Samsung Electronics Co., Ltd. makes no representation or warranties
//	with respect to the performance of this computer program, and
//	specifically disclaims any responsibility for any damages,
//	special or consequential, connected with the use of this program.
//
///////////////////////////////////////////////////////////////
//
//	REVISION HISTORY
//
//	2006.10.19	dodan2([e-mail])
//				Draft Version
//
///////////////////////////////////////////////////////////////

#ifndef __S3C6410_FIL_H__
#define __S3C6410_FIL_H__

#ifndef _FIL_H_
#include <FIL.H>
#endif

////////////////////////////////////////////////
// SFR Bit Field Macro
////////////////////////////////////////////////

// NFCONF
#define NF_NANDBOOT	(0x1<<31)
#define NF_1BIT_ECC		(0x0<<24)
#define NF_4BIT_ECC		(0x1<<24)
#define NF_8BIT_ECC		(0x1<<23)
#define NF_MASK_ECC_BIT_INDICATES   (0x3<<23)
#define NF_8BIT_ECC_STOP_BIT	    (0x1<11)
#define NF_TACLS(n)		(((n)&0x7)<<12)
#define NF_TWRPH0(n)	(((n)&0x7)<<8)
#define NF_TWRPH1(n)	(((n)&0x7)<<4)

// NFCONT
#define NF_4BIT_ECC_DEC		(0x0<<18)
#define NF_4BIT_ECC_ENC		(0x1<<18)
#define NF_LOCK_TIGHT_EN		(0x1<<17)
#define NF_SOFT_LOCK_EN		(0x1<<16)
#define NF_ECC_ENC_INT_EN		(0x1<<13)
#define NF_ECC_DEC_INT_EN		(0x1<<12)
#define NF_ILLACC_INT_EN		(0x1<<10)
#define NF_RNB_INT_EN			(0x1<<9)
#define NF_RNB_DETECT_RISE		(0x0<<8)
#define NF_RNB_DETECT_FALL		(0x1<<8)
#define NF_MAIN_ECC_UNLOCK	(0x0<<7)
#define NF_MAIN_ECC_LOCK		(0x1<<7)
#define NF_SPARE_ECC_UNLOCK	(0x0<<6)
#define NF_SPARE_ECC_LOCK		(0x1<<6)
#define NF_INIT_MECC			(0x1<<5)
#define NF_INIT_SECC			(0x1<<4)
#define NF_NFCE1				(0x1<<2)
#define NF_NFCE0				(0x1<<1)
#define NF_NFCON_DIS			(0x0)
#define NF_NFCON_EN			(0x1)

// NFCCMD
// NFADDR
// NFDATA
// NFMECCD0
// NFMECCD1
// NFSECCD
// NFSBLK
// NFEBLK

// NFSTAT
#define NF_ECC_ENC_DONE	(0x1<<7)
#define NF_ECC_DEC_DONE	(0x1<<6)
#define NF_ILLEGAL_ACCESS	(0x1<<5)
#define NF_RNB_TRANS            (0x1<<4)
#define NF_NFCE1_HI			(0x1<<3)
#define NF_NFCE0_HI			(0x1<<2)
#define NF_RNB_BUSY			(0x0)
#define NF_RNB_READY		(0x1)

// NFECCERR0
// NFECCERR1
// NFMECC0
// NFMECC1
// NFSECC
// NFMLCBITPT

#define NF_8IBTECC_DEC_DONE (0x1<<31)
///////////////////////////////////////////////
// NAND Controller Macro
///////////////////////////////////////////////
#define NF_CE_L(bank)		{	\
								if (bank == 0) pNANDFConReg->NFCONT &= ~NF_NFCE0;	\
								else if (bank == 1) pNANDFConReg->NFCONT &= ~NF_NFCE1;	\
							}
#define NF_CE_H(bank)		{	\
								if (bank == 0) pNANDFConReg->NFCONT |= NF_NFCE0;	\
								else if (bank == 1) pNANDFConReg->NFCONT |= NF_NFCE1;		\
							}
#define NF_CMD(cmd)			(pNANDFConReg->NFCMD = (UINT8)cmd)
#define NF_ADDR(addr)		(pNANDFConReg->NFADDR = (UINT8)addr)
#define NF_DATA_R()			(pNANDFConReg->NFDATA)
#define NF_DATA_R4()		(*(volatile UINT32 *)((UINT32)pNANDFConReg+0x10))
#define NF_DATA_W(data)		(pNANDFConReg->NFDATA = (UINT8)data)
#define NF_DATA_W4(data)	(*(volatile UINT32 *)((UINT32)pNANDFConReg+0x10) = (UINT32)data)
#define NF_SET_ECC_DEC()	(pNANDFConReg->NFCONT &= ~NF_4BIT_ECC_ENC)
#define NF_SET_ECC_ENC()	(pNANDFConReg->NFCONT |= NF_4BIT_ECC_ENC)
#define NF_MECC_Reset()		(pNANDFConReg->NFCONT |= NF_INIT_MECC)
#define NF_MECC_Lock()		(pNANDFConReg->NFCONT |= NF_MAIN_ECC_LOCK)
#define NF_MECC_UnLock()	(pNANDFConReg->NFCONT &= ~NF_MAIN_ECC_LOCK)
#define NF_SECC_Reset()		(pNANDFConReg->NFCONT |= NF_INIT_SECC)
#define NF_SECC_Lock()		(pNANDFConReg->NFCONT |= NF_SPARE_ECC_LOCK)
#define NF_SECC_UnLock()	(pNANDFConReg->NFCONT &= ~NF_SPARE_ECC_LOCK)

#define NF_8BIT_ECC_STOP()	(pNANDFConReg->NFCONT |= NF_8BIT_ECC_STOP_BIT)
#define NF_8BIT_ECC_STOP_CLEAR() (pNANDFConReg->NFCONT &= ~NF_8BIT_ECC_STOP_BIT)
#define NF_MECC0()			(pNANDFConReg->NFMECC0)
#define NF_MECC1()			(pNANDFConReg->NFMECC1)
#define NF_CLEAR_ECC_ENC_DONE()	(pNANDFConReg->NFSTAT |= NF_ECC_ENC_DONE)
#define NF_CLEAR_ECC_DEC_DONE()	(pNANDFConReg->NFSTAT |= NF_ECC_DEC_DONE)
#define NF_WAIT_ECC_ENC_DONE()	{	\
										while(!(pNANDFConReg->NFSTAT&NF_ECC_ENC_DONE));	\
									}

#if 0
#define NF_WAIT_ECC_DEC_DONE()	{	\
										while(!(pNANDFConReg->NFSTAT&NF_ECC_DEC_DONE));	\
									}
#endif
#define NF_WAIT_8BITECC_DEC_DONE()	{	\
										while((pNANDFConReg->NF8ECCERR0&NF_8IBTECC_DEC_DONE));	\
									}

#define NF_ECC_DEC_ERROR()			((pNANDFConReg->NFECCERR0>>26)&0x7)
#define NF_ECC_ERR0()				(pNANDFConReg->NFECCERR0)
#define NF_ECC_ERR1()				(pNANDFConReg->NFECCERR1)
#define NF_ECC_ERR_PATTERN()		(pNANDFConReg->NFMLCBITPT)

#define NF_8MECC0()			(pNANDFConReg->NFM8ECC0)
#define NF_8MECC1()			(pNANDFConReg->NFM8ECC1)
#define NF_8MECC2()			(pNANDFConReg->NFM8ECC2)
#define NF_8MECC3()			(pNANDFConReg->NFM8ECC3)

#define NF_8ECC_ERR0()				(pNANDFConReg->NF8ECCERR0)
#define NF_8ECC_ERR1()				(pNANDFConReg->NF8ECCERR1)
#define NF_8ECC_ERR2()				(pNANDFConReg->NF8ECCERR2)

#define NF_8ECC_ERR_PATTERN0()		(pNANDFConReg->NFMLC8BITPT0)
#define NF_8ECC_ERR_PATTERN1()		(pNANDFConReg->NFMLC8BITPT1)
#define NF_DETECT_RB()			{ while((pNANDFConReg->NFSTAT&0x11)!=0x11);} // RnB_Transdetect & RnB

#if	0	// Busy Check using RnB Pin
#define NF_WAIT_RnB(bank)	{	\
								while(!(pNANDFConReg->NFSTAT&NF_RNB_READY));	\
							}
#else	// Busy Check using I/O[6] Pin (Need Dummy READ Command)
#define NF_WAIT_RnB(bank)	{	\
								NF_CMD(CMD_READ_STATUS);		\
								while(!(NF_DATA_R()&0x40));		\
							}
#endif
#define NF_SET_ADDR(nPpn, nOffset)	{	\
										NF_ADDR(nOffset&0xFF);			\
										NF_ADDR((nOffset>>8)&0xFF);		\
										NF_ADDR(nPpn&0xFF);			\
										NF_ADDR((nPpn>>8)&0xFF);		\