📄 kitlusbser.h
字号:
//==============================================================================================
// Device Mode Registers
//------------------------------------------------
// Device Global Registers
DCFG = (USBOTG_LINK_BASE + 0x800), // Device Configuration
DCTL = (USBOTG_LINK_BASE + 0x804), // Device Control
DSTS = (USBOTG_LINK_BASE + 0x808), // Device Status
DIEPMSK = (USBOTG_LINK_BASE + 0x810), // Device IN Endpoint Common Interrupt Mask
DOEPMSK = (USBOTG_LINK_BASE + 0x814), // Device OUT Endpoint Common Interrupt Mask
DAINT = (USBOTG_LINK_BASE + 0x818), // Device All Endpoints Interrupt
DAINTMSK = (USBOTG_LINK_BASE + 0x81C), // Device All Endpoints Interrupt Mask
DTKNQR1 = (USBOTG_LINK_BASE + 0x820), // Device IN Token Sequence Learning Queue Read 1
DTKNQR2 = (USBOTG_LINK_BASE + 0x824), // Device IN Token Sequence Learning Queue Read 2
DVBUSDIS = (USBOTG_LINK_BASE + 0x828), // Device VBUS Discharge Time
DVBUSPULSE = (USBOTG_LINK_BASE + 0x82C), // Device VBUS Pulsing Time
DTKNQR3 = (USBOTG_LINK_BASE + 0x830), // Device IN Token Sequence Learning Queue Read 3
DTKNQR4 = (USBOTG_LINK_BASE + 0x834), // Device IN Token Sequence Learning Queue Read 4
//------------------------------------------------
// Device Logical IN Endpoint-Specific Registers
DIEPCTL0 = (USBOTG_LINK_BASE + 0x900), // Device IN Endpoint 0 Control
DIEPINT0 = (USBOTG_LINK_BASE + 0x908), // Device IN Endpoint 0 Interrupt
DIEPTSIZ0 = (USBOTG_LINK_BASE + 0x910), // Device IN Endpoint 0 Transfer Size
DIEPDMA0 = (USBOTG_LINK_BASE + 0x914), // Device IN Endpoint 0 DMA Address
//------------------------------------------------
// Device Logical OUT Endpoint-Specific Registers
DOEPCTL0 = (USBOTG_LINK_BASE + 0xB00), // Device OUT Endpoint 0 Control
DOEPINT0 = (USBOTG_LINK_BASE + 0xB08), // Device OUT Endpoint 0 Interrupt
DOEPTSIZ0 = (USBOTG_LINK_BASE + 0xB10), // Device OUT Endpoint 0 Transfer Size
DOEPDMA0 = (USBOTG_LINK_BASE + 0xB14), // Device OUT Endpoint 0 DMA Address
//------------------------------------------------
PCGCCTL = (USBOTG_LINK_BASE + 0x0E00),
// Endpoint FIFO address
EP0_FIFO = (USBOTG_LINK_BASE + 0x1000)
};
enum BULK_IN_EP_CSR
{
bulkIn_DIEPCTL = (DIEPCTL0 + 0x20*BULK_IN_EP),
bulkIn_DIEPINT = (DIEPINT0 + 0x20*BULK_IN_EP),
bulkIn_DIEPTSIZ = (DIEPTSIZ0 + 0x20*BULK_IN_EP),
bulkIn_DIEPDMA = (DIEPDMA0 + 0x20*BULK_IN_EP)
};
enum BULK_OUT_EP_CSR
{
bulkOut_DOEPCTL = (DOEPCTL0 + 0x20*BULK_OUT_EP),
bulkOut_DOEPINT = (DOEPINT0 + 0x20*BULK_OUT_EP),
bulkOut_DOEPTSIZ = (DOEPTSIZ0 + 0x20*BULK_OUT_EP),
bulkOut_DOEPDMA = (DOEPDMA0 + 0x20*BULK_OUT_EP)
};
enum EP_FIFO_ADDR
{
control_EP_FIFO = (EP0_FIFO + 0x1000*CONTROL_EP),
bulkIn_EP_FIFO = (EP0_FIFO + 0x1000*BULK_IN_EP),
bulkOut_EP_FIFO = (EP0_FIFO + 0x1000*BULK_OUT_EP)
};
//==========================
// OTG PHY CORE REGISTERS
//==========================
enum OTGPHYC_REG
{
PHYPWR = (USBOTG_PHY_BASE+0x00),
PHYCTRL = (USBOTG_PHY_BASE+0x04),
RSTCON = (USBOTG_PHY_BASE+0x08)
};
//==============================================================================================
// definitions related to Standard Device Requests
enum EP_INDEX
{
EP0, EP1, EP2, EP3, EP4
};
//------------------------------------------------
// EP0 state
enum EP0_STATE
{
EP0_STATE_INIT = 0,
EP0_STATE_GD_DEV_0 = 11,
EP0_STATE_GD_DEV_1 = 12,
EP0_STATE_GD_DEV_2 = 13,
EP0_STATE_GD_CFG_0 = 21,
EP0_STATE_GD_CFG_1 = 22,
EP0_STATE_GD_CFG_2 = 23,
EP0_STATE_GD_CFG_3 = 24,
EP0_STATE_GD_CFG_4 = 25,
EP0_STATE_GD_STR_I0 = 30,
EP0_STATE_GD_STR_I1 = 31,
EP0_STATE_GD_STR_I2 = 32,
EP0_STATE_GD_DEV_QUALIFIER = 33,
EP0_STATE_INTERFACE_GET = 34,
EP0_STATE_GET_STATUS0 = 35,
EP0_STATE_GET_STATUS1 = 36,
EP0_STATE_GET_STATUS2 = 37,
EP0_STATE_GET_STATUS3 = 38,
EP0_STATE_GET_STATUS4 = 39,
EP0_STATE_GD_CFG_ONLY_0 = 41,
EP0_STATE_GD_CFG_ONLY_1 = 42,
EP0_STATE_GD_IF_ONLY_0 = 44,
EP0_STATE_GD_IF_ONLY_1 = 45,
EP0_STATE_GD_EP0_ONLY_0 = 46,
EP0_STATE_GD_EP1_ONLY_0 = 47,
EP0_STATE_GD_EP2_ONLY_0 = 48,
EP0_STATE_GD_EP3_ONLY_0 = 49
};
// SPEC1.1
// Standard bmRequestType (direction)
// #define DEVICE_bmREQUEST_TYPE(oDeviceRequest) ((m_poDeviceRequest->bmRequestType) & 0x80)
enum DEV_REQUEST_DIRECTION
{
HOST_TO_DEVICE = 0x00,
DEVICE_TO_HOST = 0x80
};
// Standard bmRequestType (Type)
// #define DEVICE_bmREQUEST_TYPE(oDeviceRequest) ((m_poDeviceRequest->bmRequestType) & 0x60)
enum DEV_REQUEST_TYPE
{
STANDARD_TYPE = 0x00,
CLASS_TYPE = 0x20,
VENDOR_TYPE = 0x40,
RESERVED_TYPE = 0x60
};
// Standard bmRequestType (Recipient)
// #define DEVICE_bmREQUEST_RECIPIENT(oDeviceRequest) ((m_poDeviceRequest->bmRequestType) & 0x07)
enum DEV_REQUEST_RECIPIENT
{
DEVICE_RECIPIENT = 0,
INTERFACE_RECIPIENT = 1,
ENDPOINT_RECIPIENT = 2,
OTHER_RECIPIENT = 3
};
// Standard bRequest codes
enum STANDARD_REQUEST_CODE
{
STANDARD_GET_STATUS = 0,
STANDARD_CLEAR_FEATURE = 1,
STANDARD_RESERVED_1 = 2,
STANDARD_SET_FEATURE = 3,
STANDARD_RESERVED_2 = 4,
STANDARD_SET_ADDRESS = 5,
STANDARD_GET_DESCRIPTOR = 6,
STANDARD_SET_DESCRIPTOR = 7,
STANDARD_GET_CONFIGURATION = 8,
STANDARD_SET_CONFIGURATION = 9,
STANDARD_GET_INTERFACE = 10,
STANDARD_SET_INTERFACE = 11,
STANDARD_SYNCH_FRAME = 12
};
// Descriptor types
enum DESCRIPTOR_TYPE
{
DEVICE_DESCRIPTOR = 1,
CONFIGURATION_DESCRIPTOR = 2,
STRING_DESCRIPTOR = 3,
INTERFACE_DESCRIPTOR = 4,
ENDPOINT_DESCRIPTOR = 5,
DEVICE_QUALIFIER = 6,
OTHER_SPEED_CONFIGURATION = 7,
INTERFACE_POWER = 8
};
// configuration descriptor: bmAttributes
enum CONFIG_ATTRIBUTES
{
CONF_ATTR_DEFAULT = 0x80, // in Spec 1.0, it was BUSPOWERED bit.
CONF_ATTR_REMOTE_WAKEUP = 0x20,
CONF_ATTR_SELFPOWERED = 0x40
};
// endpoint descriptor
enum ENDPOINT_ATTRIBUTES
{
EP_ADDR_IN = 0x80,
EP_ADDR_OUT = 0x00,
EP_ATTR_CONTROL = 0x0,
EP_ATTR_ISOCHRONOUS = 0x1,
EP_ATTR_BULK = 0x2,
EP_ATTR_INTERRUPT = 0x3
};
// Descriptor size
enum DESCRIPTOR_SIZE
{
DEVICE_DESC_SIZE = 18,
STRING_DESC0_SIZE = 4,
STRING_DESC1_SIZE = 22,
STRING_DESC2_SIZE = 44,
CONFIG_DESC_SIZE = 9,
INTERFACE_DESC_SIZE = 9,
ENDPOINT_DESC_SIZE = 7,
DEVICE_QUALIFIER_SIZE = 10,
OTHER_SPEED_CFG_SIZE = 9
};
#define CONFIG_DESC_TOTAL_SIZE (CONFIG_DESC_SIZE+INTERFACE_DESC_SIZE+ENDPOINT_DESC_SIZE*2)
//32 <cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>
//=====================================================================
//definitions related to CSR setting
// GOTGCTL
#define B_SESSION_VALID (0x1<<19)
#define A_SESSION_VALID (0x1<<18)
// GAHBCFG
#define PTXFE_HALF (0<<8)
#define PTXFE_ZERO (1<<8)
#define NPTXFE_HALF (0<<7)
#define NPTXFE_ZERO (1<<7)
#define MODE_SLAVE (0<<5)
#define MODE_DMA (1<<5)
#define BURST_SINGLE (0<<1)
#define BURST_INCR (1<<1)
#define BURST_INCR4 (3<<1)
#define BURST_INCR8 (5<<1)
#define BURST_INCR16 (7<<1)
#define GBL_INT_UNMASK (1<<0)
#define GBL_INT_MASK (0<<0)
// GRSTCTL
#define AHB_MASTER_IDLE (0x1<<31)
#define CORE_SOFT_RESET (0x1<<0)
// GINTSTS/GINTMSK core interrupt register
#define INT_RESUME (0x1<<31)
#define INT_DISCONN (0x1<<29)
#define INT_CONN_ID_STS_CNG (0x1<<28)
#define INT_OUT_EP (0x1<<19)
#define INT_IN_EP (0x1<<18)
#define INT_ENUMDONE (0x1<<13)
#define INT_RESET (0x1<<12)
#define INT_SUSPEND (0x1<<11)
#define INT_TX_FIFO_EMPTY (0x1<<5)
#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
#define INT_SOF (0x1<<3)
#define INT_DEV_MODE (0x0<<0)
#define INT_HOST_MODE (0x1<<1)
// GRXSTSP STATUS
#define OUT_PKT_RECEIVED (0x2<<17)
#define SETUP_PKT_RECEIVED (0x6<<17)
// DCTL device control register
#define NORMAL_OPERATION (0x1<<0)
#define SOFT_DISCONNECT (0x1<<1)
// DAINT device all endpoint interrupt register
#define INT_IN_EP0 (0x1<<0)
#define INT_IN_EP1 (0x1<<1)
#define INT_IN_EP3 (0x1<<3)
#define INT_OUT_EP0 (0x1<<16)
#define INT_OUT_EP2 (0x1<<18)
#define INT_OUT_EP4 (0x1<<20)
// DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register
#define DEPCTL_EPENA (0x1<<31)
#define DEPCTL_EPDIS (0x1<<30)
#define DEPCTL_SNAK (0x1<<27)
#define DEPCTL_CNAK (0x1<<26)
#define DEPCTL_CTRL_TYPE (EP_TYPE_CONTROL<<18)
#define DEPCTL_ISO_TYPE (EP_TYPE_ISOCHRONOUS<<18)
#define DEPCTL_BULK_TYPE (EP_TYPE_BULK<<18)
#define DEPCTL_INTR_TYPE (EP_TYPE_INTERRUPT<<18)
#define DEPCTL_USBACTEP (0x1<<15)
#define DEPCTL0_MPS_64 (0x0<<0)
#define DEPCTL0_MPS_32 (0x1<<0)
#define DEPCTL0_MPS_16 (0x2<<0)
#define DEPCTL0_MPS_8 (0x3<<0)
// DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register
// DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register
// DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register
#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
#define INTKN_TXFEMP (0x1<<4)
#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
#define AHB_ERROR (0x1<<2)
#define TRANSFER_DONE (0x1<<0)
// end // from otg_dev.c
// start // from sync.h
#if 1
#define Outp32Inform(No_Reg, data) (*(volatile UINT32 *)(0xB2A0FA00 + 4*No_Reg) = (data))
#define Inp32Inform(No_Reg) (*(volatile UINT32 *)(0xB2A0FA00 + 4*No_Reg))
#define Outp32SYSC(Offset, data) (*(volatile UINT32 *)(0xB2A0F000 + Offset) = (data))
#define Inp32SYSC(Offset) (*(volatile UINT32 *)(0xB2A0F000 + Offset))
#else
#define Outp32Inform(No_Reg, data) (*(volatile UINT32 *)(OALPAtoVA(0x7E00FA00, FALSE) + 4*No_Reg) = (data))
#define Inp32Inform(No_Reg) (*(volatile UINT32 *)(OALPAtoVA(0x7E00FA00, FALSE) + 4*No_Reg))
#define Outp32SYSC(Offset, data) (*(volatile UINT32 *)(OALPAtoVA(0x7E00F000, FALSE) + Offset) = (data))
#define Inp32SYSC(Offset) (*(volatile UINT32 *)(OALPAtoVA(0x7E00F000, FALSE) + Offset))
#endif
// end // from sync.h
#endif // _KITL_USB_SERIAL_H_.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -