off.c

6410BSP1

    *pBuffer++ = pDMACReg->DMACC3Control1;
    *pBuffer++ = pDMACReg->DMACC3Configuration;

    *pBuffer++ = pDMACReg->DMACC4SrcAddr;
    *pBuffer++ = pDMACReg->DMACC4DestAddr;
    *pBuffer++ = pDMACReg->DMACC4LLI;
    *pBuffer++ = pDMACReg->DMACC4Control0;
    *pBuffer++ = pDMACReg->DMACC4Control1;
    *pBuffer++ = pDMACReg->DMACC4Configuration;

    *pBuffer++ = pDMACReg->DMACC5SrcAddr;
    *pBuffer++ = pDMACReg->DMACC5DestAddr;
    *pBuffer++ = pDMACReg->DMACC5LLI;
    *pBuffer++ = pDMACReg->DMACC5Control0;
    *pBuffer++ = pDMACReg->DMACC5Control1;
    *pBuffer++ = pDMACReg->DMACC5Configuration;

    *pBuffer++ = pDMACReg->DMACC6SrcAddr;
    *pBuffer++ = pDMACReg->DMACC6DestAddr;
    *pBuffer++ = pDMACReg->DMACC6LLI;
    *pBuffer++ = pDMACReg->DMACC6Control0;
    *pBuffer++ = pDMACReg->DMACC6Control1;
    *pBuffer++ = pDMACReg->DMACC6Configuration;

    *pBuffer++ = pDMACReg->DMACC7SrcAddr;
    *pBuffer++ = pDMACReg->DMACC7DestAddr;
    *pBuffer++ = pDMACReg->DMACC7LLI;
    *pBuffer++ = pDMACReg->DMACC7Control0;
    *pBuffer++ = pDMACReg->DMACC7Control1;
    *pBuffer++ = pDMACReg->DMACC7Configuration;
}

static void S3C6410_RestoreState_DMACon(void *pDMAC, UINT32 *pBuffer)
{
    volatile S3C6410_DMAC_REG *pDMACReg;

    pDMACReg = (S3C6410_DMAC_REG *)pDMAC;

    //DMACIntStatus;            // Read-Only
    //DMACIntTCStatus;        // Read-Only
    //DMACIntTCClear;        // Clear Register
    //DMACIntErrStatus;        // Read-Only
    //DMACIntErrClear;        // Clear Register
    //DMACRawIntTCStatus;    // Read-Only
    //DMACRawIntErrStatus;    // Read-Only
    //DMACEnbldChns;        // Read-Only

    //DMACSoftBReq;            // No use
    //DMACSoftSReq;            // No use
    //DMACSoftLBReq;        // No use
    //DMACSoftLSReq;        // No use

    pDMACReg->DMACConfiguration = *pBuffer++;
    pDMACReg->DMACSync = *pBuffer++;

    pDMACReg->DMACC0SrcAddr = *pBuffer++;
    pDMACReg->DMACC0DestAddr = *pBuffer++;
    pDMACReg->DMACC0LLI = *pBuffer++;
    pDMACReg->DMACC0Control0 = *pBuffer++;
    pDMACReg->DMACC0Control1 = *pBuffer++;
    pDMACReg->DMACC0Configuration = *pBuffer++;

    pDMACReg->DMACC1SrcAddr = *pBuffer++;
    pDMACReg->DMACC1DestAddr = *pBuffer++;
    pDMACReg->DMACC1LLI = *pBuffer++;
    pDMACReg->DMACC1Control0 = *pBuffer++;
    pDMACReg->DMACC1Control1 = *pBuffer++;
    pDMACReg->DMACC1Configuration = *pBuffer++;

    pDMACReg->DMACC2SrcAddr = *pBuffer++;
    pDMACReg->DMACC2DestAddr = *pBuffer++;
    pDMACReg->DMACC2LLI = *pBuffer++;
    pDMACReg->DMACC2Control0 = *pBuffer++;
    pDMACReg->DMACC2Control1 = *pBuffer++;
    pDMACReg->DMACC2Configuration = *pBuffer++;

    pDMACReg->DMACC3SrcAddr = *pBuffer++;
    pDMACReg->DMACC3DestAddr = *pBuffer++;
    pDMACReg->DMACC3LLI = *pBuffer++;
    pDMACReg->DMACC3Control0 = *pBuffer++;
    pDMACReg->DMACC3Control1 = *pBuffer++;
    pDMACReg->DMACC3Configuration = *pBuffer++;

    pDMACReg->DMACC4SrcAddr = *pBuffer++;
    pDMACReg->DMACC4DestAddr = *pBuffer++;
    pDMACReg->DMACC4LLI = *pBuffer++;
    pDMACReg->DMACC4Control0 = *pBuffer++;
    pDMACReg->DMACC4Control1 = *pBuffer++;
    pDMACReg->DMACC4Configuration = *pBuffer++;

    pDMACReg->DMACC5SrcAddr = *pBuffer++;
    pDMACReg->DMACC5DestAddr = *pBuffer++;
    pDMACReg->DMACC5LLI = *pBuffer++;
    pDMACReg->DMACC5Control0 = *pBuffer++;
    pDMACReg->DMACC5Control1 = *pBuffer++;
    pDMACReg->DMACC5Configuration = *pBuffer++;

    pDMACReg->DMACC6SrcAddr = *pBuffer++;
    pDMACReg->DMACC6DestAddr = *pBuffer++;
    pDMACReg->DMACC6LLI = *pBuffer++;
    pDMACReg->DMACC6Control0 = *pBuffer++;
    pDMACReg->DMACC6Control1 = *pBuffer++;
    pDMACReg->DMACC6Configuration = *pBuffer++;

    pDMACReg->DMACC7SrcAddr = *pBuffer++;
    pDMACReg->DMACC7DestAddr = *pBuffer++;
    pDMACReg->DMACC7LLI = *pBuffer++;
    pDMACReg->DMACC7Control0 = *pBuffer++;
    pDMACReg->DMACC7Control1 = *pBuffer++;
    pDMACReg->DMACC7Configuration = *pBuffer++;
}

//--------------------------------------------------------------------
//48MHz clock source for usb host1.1, IrDA, hsmmc, spi is shared with otg phy clock.
//So, initialization and reset of otg phy shoud be done on initial booting time.
//--------------------------------------------------------------------
void InitializeOTGCLK(void)
{
    volatile S3C6410_SYSCON_REG *pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
    volatile OTG_PHY_REG *pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);

    pSysConReg->HCLK_GATE |= (1<<20);

    pSysConReg->OTHERS |= (1<<16);

    pOtgPhyReg->OPHYPWR = 0x0;  // OTG block, & Analog bock in PHY2.0 power up, normal operation
    pOtgPhyReg->OPHYCLK = 0x20; // Externel clock/oscillator, 48MHz reference clock for PLL
    pOtgPhyReg->ORSTCON = 0x1;
    OALStall_ms(1);
    pOtgPhyReg->ORSTCON = 0x0;
    OALStall_ms(1);

    pSysConReg->HCLK_GATE &= ~(1<<20);

}

//------------------------------------------------------------------------------
//
// Function:     OEMPowerOff
//
// Description:  Called when the system is to transition to it's lowest  power mode (off)
//
//
void OEMPowerOff()
{
    volatile S3C6410_SYSCON_REG *pSysConReg;
    volatile S3C6410_GPIO_REG *pGPIOReg;
    volatile S3C6410_VIC_REG *pVIC0Reg;
    volatile S3C6410_VIC_REG *pVIC1Reg;
    volatile S3C6410_DMAC_REG *pDMAC0Reg;
    volatile S3C6410_DMAC_REG *pDMAC1Reg;
    volatile OTG_PHY_REG *pOtgPhyReg;

    int nIndex = 0;

    OALMSG(TRUE, (L"[OEM] ++OEMPowerOff()"));

#if 0
    // Make sure that KITL is powered off
    pArgs = (OAL_KITL_ARGS*)OALArgsQuery(OAL_ARGS_QUERY_KITL);
    if ((pArgs->flags & OAL_KITL_FLAGS_ENABLED) != 0)
    {
        OALKitlPowerOff();
        OALMSG(OAL_VERBOSE, (L"OEMPowerOff: KITL Disabled\r\n"));
    }
#endif

    //-----------------------------
    // Prepare Specific Actions for Sleep
    //-----------------------------
    BSPPowerOff();

    //------------------------------
    // Prepare CPU Entering Sleep Mode
    //------------------------------

    //----------------
    // Map SFR Address
    //----------------
    pSysConReg = (S3C6410_SYSCON_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_SYSCON, FALSE);
    pGPIOReg = (S3C6410_GPIO_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_GPIO, FALSE);
    pVIC0Reg = (S3C6410_VIC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_VIC0, FALSE);
    pVIC1Reg = (S3C6410_VIC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_VIC1, FALSE);
    pDMAC0Reg = (S3C6410_DMAC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_DMA0, FALSE);
    pDMAC1Reg = (S3C6410_DMAC_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_DMA1, FALSE);
    pOtgPhyReg = (OTG_PHY_REG *)OALPAtoVA(S3C6410_BASE_REG_PA_USBOTG_PHY, FALSE);

    //------------------
    // Save VIC Registers
    //------------------
    S3C6410_SaveState_VIC((void *)pVIC0Reg, (void *)pVIC1Reg, g_aSleepSave_VIC);

    // Disable All Interrupt
    pVIC0Reg->VICINTENCLEAR = 0xFFFFFFFF;
    pVIC1Reg->VICINTENCLEAR = 0xFFFFFFFF;
    pVIC0Reg->VICSOFTINTCLEAR = 0xFFFFFFFF;
    pVIC1Reg->VICSOFTINTCLEAR = 0xFFFFFFFF;

    //--------------------
    // Save DMAC Registers
    //--------------------
    S3C6410_SaveState_DMACon((void *)pDMAC0Reg, g_aSleepSave_DMACon0);
    S3C6410_SaveState_DMACon((void *)pDMAC1Reg, g_aSleepSave_DMACon1);

    //------------------
    // Save GPIO Register
    //------------------
    S3C6410_SaveState_GPIO((void *)pGPIOReg, g_aSleepSave_GPIO);

    //--------------------
    // Save SysCon Register
    //--------------------
    S3C6410_SaveState_SysCon((void *)pSysConReg, g_aSleepSave_SysCon);

    //---------------------------------------------------------------------------
    // Unmask Clock Gating for All IPsand Block Power turn On for the IPs not going to sleep
    //---------------------------------------------------------------------------
    // HCLK_IROM, HCLK_MEM1, HCLK_MEM0, HCLK_MFC Should be Always On for power Mode (Something coupled with BUS operation)
    //pSysConReg->HCLK_GATE |= ((1<<25)|(1<<22)|(1<<21)|(1<<0));
    pSysConReg->HCLK_GATE = 0xFFFFFFFF;
    pSysConReg->PCLK_GATE = 0xFFFFFFFF;
    pSysConReg->SCLK_GATE = 0xFFFFFFFF;
    // Turn On All Block Block Power
    pSysConReg->NORMAL_CFG = 0xFFFFFF00;

    // Wait for Block Power Stable
    while((pSysConReg->BLK_PWR_STAT & 0x7E) != 0x7E);

    //----------------------------
    // Wake Up Source Configuration
    //----------------------------
//    S3C6410_WakeUpSource_Configure();

    //-------------------------------
    // Extra work for Entering Sleep Mode
    //-------------------------------

    // USB Power Control
    pSysConReg->OTHERS &= ~(1<<16);    // USB Signal Mask Clear
    pGPIOReg->SPCON |= (1<<3);            // USB Tranceiver PAD to Suspend

    #ifdef _IROM_SDMMC_
    // Sleep Mode Pad Configuration. HSJANG 070926. SLPEN must be 0 to change cpcon value for reading OM.
    #else
    // Sleep Mode Pad Configuration
    pGPIOReg->SLPEN = 0x2;    // Controlled by SLPEN Bit (You Should Clear SLPEN Bit in Wake Up Process...)
    #endif

    //-----------------------
    // CPU Entering Sleep Mode
    //-----------------------

    OALCPUPowerOff();    // Now in Sleep

    //----------------------------
    // CPU Wake Up from Sleep Mode
    //----------------------------

    // Restore SysCon Register
    S3C6410_RestoreState_SysCon((void *)pSysConReg, g_aSleepSave_SysCon);

    // Restore GPIO Register
    S3C6410_RestoreState_GPIO((void *)pGPIOReg, g_aSleepSave_GPIO);

    #ifdef _IROM_SDMMC_
    // Sleep Mode Pad Configuration. HSJANG 070926. SLPEN must be 0 to change cpcon value for reading OM.
    #else
    // Sleep Mode Pad Configuration
    pGPIOReg->SLPEN = 0x2;    // Clear SLPEN Bit for Pad back to Normal Mode
    #endif

    //-----------------------
    // Restore DMAC Registers
    //-----------------------
    S3C6410_RestoreState_DMACon((void *)pDMAC0Reg, g_aSleepSave_DMACon0);
    S3C6410_RestoreState_DMACon((void *)pDMAC1Reg, g_aSleepSave_DMACon1);

    // Restore VIC Registers
    S3C6410_RestoreState_VIC((void *)pVIC0Reg, (void *)pVIC1Reg, g_aSleepSave_VIC);

    // UART Debug Port Initialize
    OEMInitDebugSerial();

    // Disable Vectored Interrupt Mode on CP15
    System_DisableVIC();

    // Enable Branch Prediction on CP15
    System_EnableBP();

    // Enable IRQ Interrupt on CP15
    System_EnableIRQ();

    // Enable FIQ Interrupt on CP15
    System_EnableFIQ();

    // Initialize System Timer
    OEMInitializeSystemTimer(RESCHED_PERIOD, OEM_COUNT_1MS, 0);

#if 0
    // Reinitialize KITL
    if ((pArgs->flags & OAL_KITL_FLAGS_ENABLED) != 0)
    {
        OALKitlPowerOn();
    }
#endif

    // USB Power Control
    InitializeOTGCLK();              // pll_powerdown, suspend mode

    pGPIOReg->SPCON &= ~(1<<3);        // USB Tranceiver PAD to Normal

    //--------------------------------------
    // Post Processing Specific Actions for Wake Up
    //--------------------------------------
    BSPPowerOn();

    OALMSG(TRUE, (L"[OEM] --OEMPowerOff()"));
}