off.c

6410BSP1

    pGPIOReg->GPECON = *pBuffer++;        // 080
    pGPIOReg->GPEDAT = *pBuffer++;        // 084
    pGPIOReg->GPEPUD = *pBuffer++;        // 088
    //GPECONSLP;                        // 08c
    //GPEPUDSLP;                        // 090

    // GPIO F
    pGPIOReg->GPFCON = *pBuffer++;        // 0a0
    pGPIOReg->GPFDAT = *pBuffer++;        // 0a4
    pGPIOReg->GPFPUD = *pBuffer++;        // 0a8
    //GPFCONSLP;                        // 0ac
    //GPFPUDSLP;                        // 0b0

    // GPIO G
    pGPIOReg->GPGCON = *pBuffer++;        // 0c0
    pGPIOReg->GPGDAT = *pBuffer++;        // 0c4
    pGPIOReg->GPGPUD = *pBuffer++;        // 0c8
    //GPGCONSLP;                        // 0cc
    //GPGPUDSLP;                        // 0d0

    // GPIO H
    pGPIOReg->GPHCON0 = *pBuffer++;    // 0e0
    pGPIOReg->GPHCON1 = *pBuffer++;    // 0e4
    pGPIOReg->GPHDAT = *pBuffer++;        // 0e8
    pGPIOReg->GPHPUD = *pBuffer++;        // 0ec
    //GPHCONSLP;                        // 0f0
    //GPHPUDSLP;                        // 0f4

    // GPIO I
    pGPIOReg->GPICON = *pBuffer++;        // 100
    pGPIOReg->GPIDAT = *pBuffer++;        // 104
    pGPIOReg->GPIPUD = *pBuffer++;        // 108
    //GPICONSLP;                        // 10c
    //GPIPUDSLP;                        // 110

    // GPIO J
    pGPIOReg->GPJCON = *pBuffer++;        // 120
    pGPIOReg->GPJDAT = *pBuffer++;        // 124
    pGPIOReg->GPJPUD = *pBuffer++;        // 128
    //GPJCONSLP;                        // 12c
    //GPJPUDSLP;                        // 130

    // GPIO K
    pGPIOReg->GPKCON0 = *pBuffer++;    // 800
    pGPIOReg->GPKCON1 = *pBuffer++;    // 804
    pGPIOReg->GPKDAT = *pBuffer++;        // 808
    pGPIOReg->GPKPUD = *pBuffer++;        // 80c

    // GPIO L
    pGPIOReg->GPLCON0 = *pBuffer++;    // 810
    pGPIOReg->GPLCON1 = *pBuffer++;    // 814
    pGPIOReg->GPLDAT = *pBuffer++;        // 818
    pGPIOReg->GPLPUD = *pBuffer++;        // 81c

    // GPIO M
    pGPIOReg->GPMCON = *pBuffer++;        // 820
    pGPIOReg->GPMDAT = *pBuffer++;        // 824
    pGPIOReg->GPMPUD = *pBuffer++;        // 828

    // GPIO N
    pGPIOReg->GPNCON = *pBuffer++;        // 830
    pGPIOReg->GPNDAT = *pBuffer++;        // 834
    pGPIOReg->GPNPUD = *pBuffer++;        // 838

    // GPIO O
    pGPIOReg->GPOCON = *pBuffer++;        // 140
    pGPIOReg->GPODAT = *pBuffer++;        // 144
    pGPIOReg->GPOPUD = *pBuffer++;        // 148
    //GPOCONSLP;                        // 14c
    //GPOPUDSLP;                        // 150

    // GPIO P
    pGPIOReg->GPPCON = *pBuffer++;        // 160
    pGPIOReg->GPPDAT = *pBuffer++;        // 164
    pGPIOReg->GPPPUD = *pBuffer++;        // 168
    //GPPCONSLP;                        // 16c
    //GPPPUDSLP;                        // 170

    // GPIO Q
    pGPIOReg->GPQCON = *pBuffer++;        // 180
    pGPIOReg->GPQDAT = *pBuffer++;        // 184
    pGPIOReg->GPQPUD = *pBuffer++;        // 188
    //GPQCONSLP;                        // 18c
    //GPQPUDSLP;                        // 190

    // Special Port Control
    pGPIOReg->SPCON = *pBuffer++;            // 1a0
    //SPCONSLP;                                // 880    // Configure for Sleep Mode

    // Memory Port Control
    pGPIOReg->MEM0CONSTOP = *pBuffer++;    // 1b0
    pGPIOReg->MEM1CONSTOP = *pBuffer++;    // 1b4

    pGPIOReg->MEM0CONSLP0 = *pBuffer++;    // 1c0
    pGPIOReg->MEM0CONSLP1 = *pBuffer++;    // 1c4
    pGPIOReg->MEM1CONSLP = *pBuffer++;        // 1c8

    pGPIOReg->MEM0DRVCON = *pBuffer++;    // 1d0
    pGPIOReg->MEM1DRVCON = *pBuffer++;    // 1d4

    // External Interrupt
    pGPIOReg->EINT12CON = *pBuffer++;        // 200
    pGPIOReg->EINT34CON = *pBuffer++;        // 204
    pGPIOReg->EINT56CON = *pBuffer++;        // 208
    pGPIOReg->EINT78CON = *pBuffer++;        // 20c
    pGPIOReg->EINT9CON = *pBuffer++;        // 210

    pGPIOReg->EINT12FLTCON = *pBuffer++;    // 220
    pGPIOReg->EINT34FLTCON = *pBuffer++;    // 224
    pGPIOReg->EINT56FLTCON = *pBuffer++;    // 228
    pGPIOReg->EINT78FLTCON = *pBuffer++;    // 22c
    pGPIOReg->EINT9FLTCON = *pBuffer++;        // 230

    pGPIOReg->EINT12MASK = *pBuffer++;        // 240
    pGPIOReg->EINT34MASK = *pBuffer++;        // 244
    pGPIOReg->EINT56MASK = *pBuffer++;        // 248
    pGPIOReg->EINT78MASK = *pBuffer++;        // 24c
    pGPIOReg->EINT9MASK = *pBuffer++;        // 250

    //EINT12PEND;                            // 260    // Do not Save Pending Bit
    //EINT34PEND;                            // 264
    //EINT56PEND;                            // 268
    //EINT78PEND;                            // 26c
    //EINT9PEND;                            // 270

    pGPIOReg->PRIORITY = *pBuffer++;        // 280
    //SERVICE;                                // 284    // Do not Save Read Only Register (But Check before enter sleep...)
    //SERVICEPEND;                            // 288    // Do not Save Pending Bit

    // External Interrupt Group 0
    pGPIOReg->EINT0CON0 = *pBuffer++;        // 900
    pGPIOReg->EINT0CON1 = *pBuffer++;        // 904

    pGPIOReg->EINT0FLTCON0 = *pBuffer++;    // 910
    pGPIOReg->EINT0FLTCON1 = *pBuffer++;    // 914
    pGPIOReg->EINT0FLTCON2 = *pBuffer++;    // 918
    pGPIOReg->EINT0FLTCON3 = *pBuffer++;    // 91c

    pGPIOReg->EINT0MASK = *pBuffer++;        // 920
    //EINT0PEND;                            // 924    // Do not Save Pending Bit

    // Sleep Mode Pad Configure Register
    //SLPEN;                                    // 930    // Configure for Sleep Mode

}

static void S3C6410_SaveState_SysCon(void *pSysCon, UINT32 *pBuffer)
{
    volatile S3C6410_SYSCON_REG *pSysConReg;

    pSysConReg = (S3C6410_SYSCON_REG *)pSysCon;

    //APLL_LOCK;        // Reconfiguration
    //MPLL_LOCK;        // Reconfiguration
    //EPLL_LOCK;        // Reconfiguration
    //APLL_CON;            // Reconfiguration
    //MPLL_CON;            // Reconfiguration
    //EPLL_CON0;        // Reconfiguration
    //EPLL_CON1;        // Reconfiguration

    *pBuffer++ = pSysConReg->CLK_SRC;
    *pBuffer++ = pSysConReg->CLK_DIV0;
    *pBuffer++ = pSysConReg->CLK_DIV1;
    *pBuffer++ = pSysConReg->CLK_DIV2;
    *pBuffer++ = pSysConReg->CLK_OUT;

    *pBuffer++ = pSysConReg->HCLK_GATE;
    *pBuffer++ = pSysConReg->PCLK_GATE;
    *pBuffer++ = pSysConReg->SCLK_GATE;

    *pBuffer++ = pSysConReg->AHB_CON0;
    *pBuffer++ = pSysConReg->AHB_CON1;
    *pBuffer++ = pSysConReg->AHB_CON2;
    *pBuffer++ = pSysConReg->SDMA_SEL;

    //SW_RST;            // Reset Trigger
    //SYS_ID;            // Read Only

    *pBuffer++ = pSysConReg->MEM_SYS_CFG;
    *pBuffer++ = pSysConReg->QOS_OVERRIDE0;
    *pBuffer++ = pSysConReg->QOS_OVERRIDE1;
    //MEM_CFG_STAT;    // Read Only

    //PWR_CFG;            // Retension
    //EINT_MASK;        // Retension
    *pBuffer++ = pSysConReg->NORMAL_CFG;    // Retension, But H/W Problem
    //STOP_CFG;            // Retension
    //SLEEP_CFG;        // Retension

    //OSC_FREQ;            // Retension
    //OSC_STABLE;        // Retension
    //PWR_STABLE;        // Retension
    //FPC_STABLE;        // Retension
    //MTC_STABLE;        // Retension

    //OTHERS;            // Retension
    //RST_STAT;            // Retension, Read Only
    //WAKEUP_STAT;        // Retension
    //BLK_PWR_STAT;        // Retension, Read Only

    //INFORM0;            // Retension
    //INFORM1;            // Retension
    //INFORM2;            // Retension
    //INFORM3;            // Retension
    //INFORM4;            // Retension
    //INFORM5;            // Retension
    //INFORM6;            // Retension
    //INFORM7;            // Retension
}

static void S3C6410_RestoreState_SysCon(void *pSysCon, UINT32 *pBuffer)
{
    volatile S3C6410_SYSCON_REG *pSysConReg;

    pSysConReg = (S3C6410_SYSCON_REG *)pSysCon;
    //APLL_LOCK;        // Reconfiguration
    //MPLL_LOCK;        // Reconfiguration
    //EPLL_LOCK;        // Reconfiguration
    //APLL_CON;            // Reconfiguration
    //MPLL_CON;            // Reconfiguration
    //EPLL_CON0;        // Reconfiguration
    //EPLL_CON1;        // Reconfiguration

    pSysConReg->CLK_SRC = *pBuffer++;
    pSysConReg->CLK_DIV0 = *pBuffer++;
    pSysConReg->CLK_DIV1 = *pBuffer++;
    pSysConReg->CLK_DIV2 = *pBuffer++;
    pSysConReg->CLK_OUT = *pBuffer++;

    pSysConReg->HCLK_GATE = *pBuffer++;
    pSysConReg->PCLK_GATE = *pBuffer++;
    pSysConReg->SCLK_GATE = *pBuffer++;

    pSysConReg->AHB_CON0 = *pBuffer++;
    pSysConReg->AHB_CON1 = *pBuffer++;
    pSysConReg->AHB_CON2 = *pBuffer++;
    pSysConReg->SDMA_SEL = *pBuffer++;

    //SW_RST;            // Reset Trigger
    //SYS_ID;            // Read Only

    pSysConReg->MEM_SYS_CFG = *pBuffer++;
    pSysConReg->QOS_OVERRIDE0 = *pBuffer++;
    pSysConReg->QOS_OVERRIDE1 = *pBuffer++;
    //MEM_CFG_STAT;    // Read Only

    //PWR_CFG;            // Retension
    //EINT_MASK;        // Retension
    pSysConReg->NORMAL_CFG = *pBuffer++;    // Retension, But H/W Problem
    //STOP_CFG;            // Retension
    //SLEEP_CFG;        // Retension

    //OSC_FREQ;            // Retension
    //OSC_STABLE;        // Retension
    //PWR_STABLE;        // Retension
    //FPC_STABLE;        // Retension
    //MTC_STABLE;        // Retension

    //OTHERS;            // Retension
    //RST_STAT;            // Retension, Read Only
    //WAKEUP_STAT;        // Retension
    //BLK_PWR_STAT;        // Retension, Read Only

    //INFORM0;            // Retension
    //INFORM1;            // Retension
    //INFORM2;            // Retension
    //INFORM3;            // Retension
    //INFORM4;            // Retension
    //INFORM5;            // Retension
    //INFORM6;            // Retension
    //INFORM7;            // Retension
}

static void S3C6410_SaveState_DMACon(void *pDMAC, UINT32 *pBuffer)
{
    volatile S3C6410_DMAC_REG *pDMACReg;

    pDMACReg = (S3C6410_DMAC_REG *)pDMAC;

    //DMACIntStatus;            // Read-Only
    //DMACIntTCStatus;        // Read-Only
    //DMACIntTCClear;        // Clear Register
    //DMACIntErrStatus;        // Read-Only
    //DMACIntErrClear;        // Clear Register
    //DMACRawIntTCStatus;    // Read-Only
    //DMACRawIntErrStatus;    // Read-Only
    //DMACEnbldChns;        // Read-Only

    //DMACSoftBReq;            // No use
    //DMACSoftSReq;            // No use
    //DMACSoftLBReq;        // No use
    //DMACSoftLSReq;        // No use

    *pBuffer++ = pDMACReg->DMACConfiguration;
    *pBuffer++ = pDMACReg->DMACSync;

    *pBuffer++ = pDMACReg->DMACC0SrcAddr;
    *pBuffer++ = pDMACReg->DMACC0DestAddr;
    *pBuffer++ = pDMACReg->DMACC0LLI;
    *pBuffer++ = pDMACReg->DMACC0Control0;
    *pBuffer++ = pDMACReg->DMACC0Control1;
    *pBuffer++ = pDMACReg->DMACC0Configuration;

    *pBuffer++ = pDMACReg->DMACC1SrcAddr;
    *pBuffer++ = pDMACReg->DMACC1DestAddr;
    *pBuffer++ = pDMACReg->DMACC1LLI;
    *pBuffer++ = pDMACReg->DMACC1Control0;
    *pBuffer++ = pDMACReg->DMACC1Control1;
    *pBuffer++ = pDMACReg->DMACC1Configuration;

    *pBuffer++ = pDMACReg->DMACC2SrcAddr;
    *pBuffer++ = pDMACReg->DMACC2DestAddr;
    *pBuffer++ = pDMACReg->DMACC2LLI;
    *pBuffer++ = pDMACReg->DMACC2Control0;
    *pBuffer++ = pDMACReg->DMACC2Control1;
    *pBuffer++ = pDMACReg->DMACC2Configuration;

    *pBuffer++ = pDMACReg->DMACC3SrcAddr;
    *pBuffer++ = pDMACReg->DMACC3DestAddr;
    *pBuffer++ = pDMACReg->DMACC3LLI;
    *pBuffer++ = pDMACReg->DMACC3Control0;