makefile

C++作业

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# IMPORTANT NOTE: use 'gmake' with this makefile
#   - this makefile uses advanced features not present in the standard unix 'make'
#   - the GNU implementation of make provides these new features in 'gmake'
#   - in order to avoid having to remember to use gmake, it is recommended
#     that you add an alias from gmake to make in your .cshrc or .profile file.
############################################################################

# The CC variable is used to specify which compiler to use.
CC       = g++

# The DEBUG variable is where debugging flags go
DEBUG    = -g

# The CFLAGS variable should contain all flags to be sent to the source-code compiler
CFLAGS   = $(DEBUG) -Wall -ansi

# The LDFLAGS variable should contain all flags to be sent to the linker
LDFLAGS  = $(DEBUG)

# Some useful location-style variables for use later on 
ROOTDIR    = .
SRCDIR     =  $(ROOTDIR)
INSTALLDIR =  $(HOME)/root

# The SRCS variable is a list of all files ending in .cc in the current directory
# (and in all subdirectories).  This may not be the action you want here.  You can
# change it to $(shell ls *.cc) for a more limited version.
SRCS       = $(shell find . -name '*.cc')

# The OBJS variable is like SRCS except that .cc is changed to .o
OBJS	   = $(SRCS:.cc=.o)

# The LIBS variable should contain any libraries that need to be included.
LIBS       = 

# The INCS variable 
INCS       =  

# The INCDIRS variable contains a list of all subdirectories of the SRCDIR.  A list
# of -I flags is formed based on this list telling the C++ compiler where to look
# for header files.
INCDIRS   := $(shell find $(SRCDIR) -type d -name '*')
CFLAGS    += $(addprefix -I,$(INCDIRS))

# The name of the executable to create (you can naturally change the name if you desire)
EXEC   = main

# This is a rule telling 'make' how to automatically create .o files from .cc files.
.cc.o:
	$(CC) -c $(CFLAGS) $<


default: $(EXEC)

# This target specifies how the executable should be made.  It
# indicates that the executable is called $(EXEC), and that it depends
# on all targets listed in $(OBJS) and $(INCS) and 'dep'.  Once all of
# those dependencies have been verified as up-to-date,
# the single compilation command is executed.
$(EXEC): $(OBJS) $(INCS) dep
	$(CC) -o $(EXEC) $(OBJS) $(LIBS)

# A target for installing
install: $(EXEC)
	cp $(EXEC) $(INSTALLDIR)

# The 'clean' target is for cleaning extraneous files.  This target should remove
# all intermediate files that can be recreated by the compilation
# process (like .o files), but should not remove the final executable(s).
clean:
	rm -f $(OBJS)

# The 'realclean' target is like 'clean' except that it removes every
# file that can be recreated, including the executables.
realclean: clean
	rm -f $(EXEC) dep

# The 'depend' target creates an automatic dependency list so that we do not
# need to manually maintain it.  It is guaranteed to execute its associated
# code each time the target is specified
depend: .FORCE
	$(CC) -MM $(INCDIRS) $(SRCS) > dep	

# The 'dep' target is like 'depend' except that it is only executed if the 'dep
# file does not already exist.
dep:
	$(CC) -MM $(INCDIRS) $(SRCS) > dep

# Currently, test does nothing.  Add whatever commands are appropriate
test:
	@echo "Test currently does nothing"

# This includes the 'dep' file, which consists of a list of .o targets
# and associated source code and header file dependencies.  It is used
# by the .o.cc rule above to determine which .o files need to be
# recompiled.  
-include dep