📄 at91m55800a.h
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AT91_REG SPI_TDR; // Transmit Data Register
AT91_REG SPI_SR; // Status Register
AT91_REG SPI_IER; // Interrupt Enable Register
AT91_REG SPI_IDR; // Interrupt Disable Register
AT91_REG SPI_IMR; // Interrupt Mask Register
AT91_REG SPI_RPR; // Receive Pointer Register
AT91_REG SPI_RCR; // Receive Counter Register
AT91_REG SPI_TPR; // Transmit Pointer Register
AT91_REG SPI_TCR; // Transmit Counter Register
AT91_REG SPI_CSR[4]; // Chip Select Register
} AT91S_SPI, *AT91PS_SPI;
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
// *****************************************************************************
typedef struct _AT91S_ADC {
AT91_REG ADC_CR; // Control Register
AT91_REG ADC_MR; // Mode Register
AT91_REG Reserved0[2]; //
AT91_REG ADC_CHER; // Channel Enable Register
AT91_REG ADC_CHDR; // Channel Disable Register
AT91_REG ADC_CHSR; // Channel Status Register
AT91_REG Reserved1[1]; //
AT91_REG ADC_SR; // Status Register
AT91_REG ADC_IER; // Interrupt Enable Register
AT91_REG ADC_IDR; // Interrupt Disable Register
AT91_REG ADC_IMR; // Interrupt Mask Register
AT91_REG ADC_CDR[4]; // Convert Data Register
} AT91S_ADC, *AT91PS_ADC;
// -------- ADC_CR : (ADC Offset: 0x0) Control Register --------
#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) Mode Register --------
#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRG ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
#define AT91C_ADC_TRG_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
#define AT91C_ADC_TRG_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
#define AT91C_ADC_TRG_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
#define AT91C_ADC_TRG_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
#define AT91C_ADC_TRG_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
#define AT91C_ADC_TRG_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
#define AT91C_ADC_TRG_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_RES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
#define AT91C_ADC_RES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
#define AT91C_ADC_RES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL ((unsigned int) 0x1F << 8) // (ADC) Prescaler rate selection
// -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register --------
#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
// -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register --------
// -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register --------
// -------- ADC_SR : (ADC Offset: 0x20) Status Register --------
#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
// -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register --------
// -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register --------
// -------- ADC_IMR : (ADC Offset: 0x2c) Interrupt Mask Register --------
// -------- ADC_CDR : (ADC Offset: 0x30) Convert Data Register --------
#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Digital to Analog Convertor
// *****************************************************************************
typedef struct _AT91S_DAC {
AT91_REG DAC_CR; // Control Register
AT91_REG DAC_MR; // Mode Register
AT91_REG DAC_DHR; // Data Holding Register
AT91_REG DAC_DOR; // Data Output Register
AT91_REG DAC_SR; // Status Register
AT91_REG DAC_IER; // Interrupt Enable Register
AT91_REG DAC_IDR; // Interrupt Disable Register
AT91_REG DAC_IMR; // Interrupt Mask Register
} AT91S_DAC, *AT91PS_DAC;
// -------- DAC_CR : (DAC Offset: 0x0) Control Register --------
#define AT91C_DAC_SWRST ((unsigned int) 0x1 << 0) // (DAC) Software Reset
// -------- DAC_MR : (DAC Offset: 0x4) Mode Register --------
#define AT91C_DAC_TTRGEN ((unsigned int) 0x1 << 0) // (DAC) Timer Trigger Enable
#define AT91C_DAC_TTRGEN_DIS ((unsigned int) 0x0) // (DAC) The data written into the Data Holding Register (DAC_DHR) is transferred one main clock cycle later to the data output register (DAC_DOR).
#define AT91C_DAC_TTRGEN_EN ((unsigned int) 0x1) // (DAC) The data transfer from the DAC_DHR to the DAC_DOR is synchronized by the timer trigger.
#define AT91C_DAC_TTRGSEL ((unsigned int) 0x7 << 1) // (DAC) Timer Trigger Selection
#define AT91C_DAC_TTRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (DAC) Selected TRGSEL = TIAO0
#define AT91C_DAC_TTRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (DAC) Selected TRGSEL = TIAO1
#define AT91C_DAC_TTRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (DAC) Selected TRGSEL = TIAO2
#define AT91C_DAC_TTRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (DAC) Selected TRGSEL = TIAO3
#define AT91C_DAC_TTRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (DAC) Selected TRGSEL = TIAO4
#define AT91C_DAC_TTRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (DAC) Selected TRGSEL = TIAO5
#define AT91C_DAC_RES ((unsigned int) 0x1 << 4) // (DAC) Resolution.
#define AT91C_DAC_RES_10_BIT ((unsigned int) 0x0 << 4) // (DAC) 10-bit resolution
#define AT91C_DAC_RES_8_BIT ((unsigned int) 0x1 << 4) // (DAC) 8-bit resolution
// -------- DAC_DHR : (DAC Offset: 0x8) Data Holding Register --------
#define AT91C_DAC_DATA ((unsigned int) 0x3FF << 0) // (DAC) Data to be Converted
// -------- DAC_DOR : (DAC Offset: 0xc) Data Output Register --------
// -------- DAC_SR : (DAC Offset: 0x10) Status Register --------
#define AT91C_DAC_DATRDY ((unsigned int) 0x1 << 0) // (DAC) Data Ready for Conversion
// -------- DAC_IER : (DAC Offset: 0x14) Data Ready for Conversion Interrupt Enable --------
// -------- DAC_IDR : (DAC Offset: 0x18) Data Ready for Conversion Interrupt Disable --------
// -------- DAC_IMR : (DAC Offset: 0x1c) Data Ready for Conversion Interrupt Mask --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Special Function Interface
// *****************************************************************************
typedef struct _AT91S_SF {
AT91_REG SF_CIDR; // Chip ID Register
AT91_REG SF_EXID; // Chip ID Extension Register
AT91_REG SF_RSR; // Reset Status Register
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