📄 lib_at91m55800a.h
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//*----------------------------------------------------------------------------
__inline void AT91F_DAC0_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_DAC0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_RTC_CfgAPMC
//* \brief Enable Peripheral clock in PMC for RTC
//*----------------------------------------------------------------------------
__inline void AT91F_RTC_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_RTC));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIOB_CfgAPMC
//* \brief Enable Peripheral clock in PMC for PIOB
//*----------------------------------------------------------------------------
__inline void AT91F_PIOB_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_PIOB));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_PIOA_CfgAPMC
//* \brief Enable Peripheral clock in PMC for PIOA
//*----------------------------------------------------------------------------
__inline void AT91F_PIOA_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_PIOA));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgAPMC
//* \brief Enable Peripheral clock in PMC for SPI
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SPI));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_SPI_CfgPIO
//* \brief Configure PIO controllers to drive SPI signals
//*----------------------------------------------------------------------------
__inline void AT91F_SPI_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA26_NPCS0 ) |
((unsigned int) AT91C_PA27_NPCS1 ) |
((unsigned int) AT91C_PA25_MOSI ) |
((unsigned int) AT91C_PA28_NPCS2 ) |
((unsigned int) AT91C_PA29_NPCS3 ) |
((unsigned int) AT91C_PA24_MISO ) |
((unsigned int) AT91C_PA23_SPCK ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_APMC_CfgAPMC
//* \brief Enable Peripheral clock in PMC for APMC
//*----------------------------------------------------------------------------
__inline void AT91F_APMC_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SLCK) |
((unsigned int) 1 << AT91C_ID_APMC));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US2_CfgAPMC
//* \brief Enable Peripheral clock in PMC for US2
//*----------------------------------------------------------------------------
__inline void AT91F_US2_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US2));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US2_CfgPIO
//* \brief Configure PIO controllers to drive US2 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US2_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA21_TXD2 ) |
((unsigned int) AT91C_PA22_RXD2 ) |
((unsigned int) AT91C_PA20_SCK2 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgAPMC
//* \brief Enable Peripheral clock in PMC for US1
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPIO
//* \brief Configure PIO controllers to drive US1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA19_RXD1 ) |
((unsigned int) AT91C_PA18_TXD1 ) |
((unsigned int) AT91C_PA17_SCK1 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgAPMC
//* \brief Enable Peripheral clock in PMC for US0
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPIO
//* \brief Configure PIO controllers to drive US0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA16_RXD0 ) |
((unsigned int) AT91C_PA15_TXD0 ) |
((unsigned int) AT91C_PA14_SCK0 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgAPMC
//* \brief Enable Peripheral clock in PMC for AIC
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_IRQ0) |
((unsigned int) 1 << AT91C_ID_FIQ) |
((unsigned int) 1 << AT91C_ID_IRQ5) |
((unsigned int) 1 << AT91C_ID_IRQ4) |
((unsigned int) 1 << AT91C_ID_IRQ3) |
((unsigned int) 1 << AT91C_ID_IRQ2) |
((unsigned int) 1 << AT91C_ID_IRQ1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPIO
//* \brief Configure PIO controllers to drive AIC signals
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA13_FIQ ) |
((unsigned int) AT91C_PA9_IRQ0 ) |
((unsigned int) AT91C_PA10_IRQ1 ) |
((unsigned int) AT91C_PA11_IRQ2 ) |
((unsigned int) AT91C_PA12_IRQ3 ), // Peripheral A
0); // Peripheral B
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
((unsigned int) AT91C_PB3_IRQ4 ) |
((unsigned int) AT91C_PB4_IRQ5 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC5_CfgAPMC
//* \brief Enable Peripheral clock in PMC for TC5
//*----------------------------------------------------------------------------
__inline void AT91F_TC5_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC5));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC4_CfgAPMC
//* \brief Enable Peripheral clock in PMC for TC4
//*----------------------------------------------------------------------------
__inline void AT91F_TC4_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC4));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC3_CfgAPMC
//* \brief Enable Peripheral clock in PMC for TC3
//*----------------------------------------------------------------------------
__inline void AT91F_TC3_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC3));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgAPMC
//* \brief Enable Peripheral clock in PMC for TC2
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC2));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgPIO
//* \brief Configure PIO controllers to drive TC2 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
((unsigned int) AT91C_PB26_TIOA2 ) |
((unsigned int) AT91C_PB27_TIOB2 ) |
((unsigned int) AT91C_PB25_TCLK2 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgAPMC
//* \brief Enable Peripheral clock in PMC for TC1
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgPIO
//* \brief Configure PIO controllers to drive TC1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
((unsigned int) AT91C_PB23_TIOA1 ) |
((unsigned int) AT91C_PB24_TIOB1 ) |
((unsigned int) AT91C_PB22_TCLK1 ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgAPMC
//* \brief Enable Peripheral clock in PMC for TC0
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgAPMC (void)
{
AT91F_APMC_EnablePeriphClock(
AT91C_BASE_APMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgPIO
//* \brief Configure PIO controllers to drive TC0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
((unsigned int) AT91C_PB20_TIOA0 ) |
((unsigned int) AT91C_PB21_TIOB0 ) |
((unsigned int) AT91C_PB19_TCLK0 ), // Peripheral A
0); // Peripheral B
}
#endif // lib_AT91M55800A_H
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