lib_at91m55800a.h

AT91M5800a例子

__inline void AT91F_US_DisableTx (
        AT91PS_USART pUSART)     // \arg pointer to a USART controller
{
    //* Disable transmitter
    pUSART->US_CR = AT91C_US_TXDIS;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Close
//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
//*----------------------------------------------------------------------------
__inline void AT91F_US_Close (
        AT91PS_USART pUSART)     // \arg pointer to a USART controller
{
    //* Reset the baud rate divisor register
    pUSART->US_BRGR = 0 ;

    //* Reset the USART mode
    pUSART->US_MR = 0  ;

    //* Reset the Timeguard Register
    pUSART->US_TTGR = 0;

    //* Disable all interrupts
    pUSART->US_IDR = 0xFFFFFFFF ;

    //* Disable receiver and transmitter and stop any activity immediately
    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_TxReady
//* \brief Return 1 if a character can be written in US_THR
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_TxReady (
        AT91PS_USART pUSART )     // \arg pointer to a USART controller
{
    return (pUSART->US_CSR & AT91C_US_TXRDY);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_RxReady
//* \brief Return 1 if a character can be read in US_RHR
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_RxReady (
        AT91PS_USART pUSART )     // \arg pointer to a USART controller
{
    return (pUSART->US_CSR & AT91C_US_RXRDY);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_Error
//* \brief Return the error flag
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_Error (
        AT91PS_USART pUSART )     // \arg pointer to a USART controller
{
    return (pUSART->US_CSR &
        (AT91C_US_OVRE |  // Overrun error
         AT91C_US_FRAME | // Framing error
         AT91C_US_PARE));  // Parity error
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_PutChar
//* \brief Send a character,does not check if ready to send
//*----------------------------------------------------------------------------
__inline void AT91F_US_PutChar (
        AT91PS_USART pUSART,
        int character )
{
    pUSART->US_THR = (character & 0x1FF);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_GetChar
//* \brief Receive a character,does not check if a character is available
//*----------------------------------------------------------------------------
__inline int AT91F_US_GetChar (
        const AT91PS_USART pUSART)
{
    return((pUSART->US_RHR) & 0x1FF);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_SendFrame
//* \brief Return 1 if PDC has been initialized with Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_SendFrame(
        AT91PS_USART pUSART,
        char *pBuffer,
        unsigned int szBuffer )
{
        return AT91F_PDC_SendFrame(
                (AT91PS_PDC) &(pUSART->US_RPR),
                pBuffer,
                szBuffer);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_US_ReceiveFrame
//* \brief Return 1 if PDC has been initialized with Buffer, 0 if PDC is busy
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_US_ReceiveFrame (
        AT91PS_USART pUSART,
        char *pBuffer,
        unsigned int szBuffer )
{
        return AT91F_PDC_ReceiveFrame(
                (AT91PS_PDC) &(pUSART->US_RPR),
                pBuffer,
                szBuffer);
}

/* *****************************************************************************
                SOFTWARE API FOR AIC
   ***************************************************************************** */
#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_ConfigureIt
//* \brief Interrupt Handler Initialization
//*----------------------------------------------------------------------------
__inline unsigned int AT91F_AIC_ConfigureIt (
        AT91PS_AIC pAic,  // \arg pointer to the AIC registers
        unsigned int irq_id,     // \arg interrupt number to initialize
        unsigned int priority,   // \arg priority to give to the interrupt
        unsigned int src_type,   // \arg activation and sense of activation
        void (*newHandler) (void) ) // \arg address of the interrupt handler
{
        unsigned int oldHandler;
    unsigned int mask ;

    oldHandler = pAic->AIC_SVR[irq_id];

    mask = 0x1 << irq_id ;
    //* Disable the interrupt on the interrupt controller
    pAic->AIC_IDCR = mask ;
    //* Save the interrupt handler routine pointer and the interrupt priority
    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
    //* Store the Source Mode Register
    pAic->AIC_SMR[irq_id] = src_type | priority  ;
    //* Clear the interrupt on the interrupt controller
    pAic->AIC_ICCR = mask ;

        return oldHandler;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_EnableIt
//* \brief Enable corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_EnableIt (
        AT91PS_AIC pAic,      // \arg pointer to the AIC registers
        unsigned int irq_id ) // \arg interrupt number to initialize
{
    //* Enable the interrupt on the interrupt controller
    pAic->AIC_IECR = 0x1 << irq_id ;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_DisableIt
//* \brief Disable corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_DisableIt (
        AT91PS_AIC pAic,      // \arg pointer to the AIC registers
        unsigned int irq_id ) // \arg interrupt number to initialize
{
    unsigned int mask = 0x1 << irq_id;
    //* Disable the interrupt on the interrupt controller
    pAic->AIC_IDCR = mask ;
    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
    pAic->AIC_ICCR = mask ;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_ClearIt
//* \brief Clear corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_ClearIt (
        AT91PS_AIC pAic,     // \arg pointer to the AIC registers
        unsigned int irq_id) // \arg interrupt number to initialize
{
    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
    pAic->AIC_ICCR = (0x1 << irq_id);
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_AcknowledgeIt
//* \brief Acknowledge corresponding IT number
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_AcknowledgeIt (
        AT91PS_AIC pAic)     // \arg pointer to the AIC registers
{
    pAic->AIC_EOICR = pAic->AIC_EOICR;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_Trig
//* \brief Trig an IT
//*----------------------------------------------------------------------------
__inline void  AT91F_AIC_Trig (
        AT91PS_AIC pAic,     // \arg pointer to the AIC registers
        unsigned int irq_id) // \arg interrupt number
{
        pAic->AIC_ISCR = (0x1 << irq_id) ;
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_IsActive
//* \brief Test if an IT is active
//*----------------------------------------------------------------------------
__inline unsigned int  AT91F_AIC_IsActive (
        AT91PS_AIC pAic,     // \arg pointer to the AIC registers
        unsigned int irq_id) // \arg Interrupt Number
{
        return (pAic->AIC_ISR & (0x1 << irq_id));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_AIC_IsPending
//* \brief Test if an IT is pending
//*----------------------------------------------------------------------------
__inline unsigned int  AT91F_AIC_IsPending (
        AT91PS_AIC pAic,     // \arg pointer to the AIC registers
        unsigned int irq_id) // \arg Interrupt Number
{
        return (pAic->AIC_IPR & (0x1 << irq_id));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_EBI_CfgPIO
//* \brief Configure PIO controllers to drive EBI signals
//*----------------------------------------------------------------------------
__inline void AT91F_EBI_CfgPIO (void)
{
	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOB, // PIO controller base address
		((unsigned int) AT91C_PB18_BMS     ), // Peripheral A
		0); // Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC1_CfgAPMC
//* \brief Enable Peripheral clock in PMC for  ADC1
//*----------------------------------------------------------------------------
__inline void AT91F_ADC1_CfgAPMC (void)
{
	AT91F_APMC_EnablePeriphClock(
		AT91C_BASE_APMC, // PIO controller base address
		((unsigned int) 1 << AT91C_ID_ADC1));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC1_CfgPIO
//* \brief Configure PIO controllers to drive ADC1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_ADC1_CfgPIO (void)
{
	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOB, // PIO controller base address
		((unsigned int) AT91C_PB7_AD1TRIG ), // Peripheral A
		0); // Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC0_CfgAPMC
//* \brief Enable Peripheral clock in PMC for  ADC0
//*----------------------------------------------------------------------------
__inline void AT91F_ADC0_CfgAPMC (void)
{
	AT91F_APMC_EnablePeriphClock(
		AT91C_BASE_APMC, // PIO controller base address
		((unsigned int) 1 << AT91C_ID_ADC0));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_ADC0_CfgPIO
//* \brief Configure PIO controllers to drive ADC0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_ADC0_CfgPIO (void)
{
	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOB, // PIO controller base address
		((unsigned int) AT91C_PB6_AD0TRIG ), // Peripheral A
		0); // Peripheral B
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_WD_CfgAPMC
//* \brief Enable Peripheral clock in PMC for  WD
//*----------------------------------------------------------------------------
__inline void AT91F_WD_CfgAPMC (void)
{
	AT91F_APMC_EnablePeriphClock(
		AT91C_BASE_APMC, // PIO controller base address
		((unsigned int) 1 << AT91C_ID_WD));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DAC1_CfgAPMC
//* \brief Enable Peripheral clock in PMC for  DAC1
//*----------------------------------------------------------------------------
__inline void AT91F_DAC1_CfgAPMC (void)
{
	AT91F_APMC_EnablePeriphClock(
		AT91C_BASE_APMC, // PIO controller base address
		((unsigned int) 1 << AT91C_ID_DAC1));
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_DAC0_CfgAPMC
//* \brief Enable Peripheral clock in PMC for  DAC0