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AT91M5800a例子

<tr><td align="CENTER" bgcolor="#FFFFCC">3..1</td><td align="CENTER"><a name="DAC_TTRGSEL"></a><b>DAC_TTRGSEL</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL">AT91C_DAC_TTRGSEL</a></font></td><td><b>Timer Trigger Selection</b><br>Only used if TTRGEN = 1<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="DAC_TTRGSEL_TIOA0"></a><b>DAC_TTRGSEL_TIOA0</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL_TIOA0">AT91C_DAC_TTRGSEL_TIOA0</a></font></td><td><br>Selected TRGSEL = TIAO0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="DAC_TTRGSEL_TIOA1"></a><b>DAC_TTRGSEL_TIOA1</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL_TIOA1">AT91C_DAC_TTRGSEL_TIOA1</a></font></td><td><br>Selected TRGSEL = TIAO1</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="DAC_TTRGSEL_TIOA2"></a><b>DAC_TTRGSEL_TIOA2</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL_TIOA2">AT91C_DAC_TTRGSEL_TIOA2</a></font></td><td><br>Selected TRGSEL = TIAO2</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="DAC_TTRGSEL_TIOA3"></a><b>DAC_TTRGSEL_TIOA3</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL_TIOA3">AT91C_DAC_TTRGSEL_TIOA3</a></font></td><td><br>Selected TRGSEL = TIAO3</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="DAC_TTRGSEL_TIOA4"></a><b>DAC_TTRGSEL_TIOA4</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL_TIOA4">AT91C_DAC_TTRGSEL_TIOA4</a></font></td><td><br>Selected TRGSEL = TIAO4</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="DAC_TTRGSEL_TIOA5"></a><b>DAC_TTRGSEL_TIOA5</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_TTRGSEL_TIOA5">AT91C_DAC_TTRGSEL_TIOA5</a></font></td><td><br>Selected TRGSEL = TIAO5</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="DAC_RES"></a><b>DAC_RES</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_RES">AT91C_DAC_RES</a></font></td><td><b>Resolution.</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="DAC_RES_10_BIT"></a><b>DAC_RES_10_BIT</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_RES_10_BIT">AT91C_DAC_RES_10_BIT</a></font></td><td><br>10-bit resolution</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="DAC_RES_8_BIT"></a><b>DAC_RES_8_BIT</b><font size="-1"><br><a href="AT91M55800A_h.html#AT91C_DAC_RES_8_BIT">AT91C_DAC_RES_8_BIT</a></font></td><td><br>8-bit resolution</td></tr>
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<a name="DAC_DHR"></a><h4><a href="#DAC">DAC</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> DAC_DHR  <i>Data Holding Register</i></h4><ul><null><font size="-2"><li><b>DAC1</b> <i><a href="AT91M55800A_h.html#AT91C_DAC1_DHR">AT91C_DAC1_DHR</a></i> 0xFFFA8008</font><font size="-2"><li><b>DAC0</b> <i><a href="AT91M55800A_h.html#AT91C_DAC0_DHR">AT91C_DAC0_DHR</a></i> 0xFFFB4008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="DAC_DATA"></a><b>DAC_DATA</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_DATA">AT91C_DAC_DATA</a></font></td><td><b>Data to be Converted</b><br>Data that is to be converted by the DAC is stored in this register. Data to be converted must be written in a right-aligned format.<br>In 8-bit resolution mode (RES = 1), data written into the Data Holding Register will be shifted to the left by 2 bits and thetwo LSBs will be 0.<br>In both 8-bit and 10-bit modes, data will be read as written after the adjustments are done. All non-significant bits read 0.</td></tr>
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<a name="DAC_DOR"></a><h4><a href="#DAC">DAC</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> DAC_DOR  <i>Data Output Register</i></h4><ul><null><font size="-2"><li><b>DAC1</b> <i><a href="AT91M55800A_h.html#AT91C_DAC1_DOR">AT91C_DAC1_DOR</a></i> 0xFFFA800C</font><font size="-2"><li><b>DAC0</b> <i><a href="AT91M55800A_h.html#AT91C_DAC0_DOR">AT91C_DAC0_DOR</a></i> 0xFFFB400C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">9..0</td><td align="CENTER"><a name="DAC_DATA"></a><b>DAC_DATA</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_DATA">AT91C_DAC_DATA</a></font></td><td><b>Data being Converted</b><br>Data being converted is stored, in a right-aligned format, in this register.All non-significant bits read 0.</td></tr>
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<a name="DAC_SR"></a><h4><a href="#DAC">DAC</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> DAC_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>DAC1</b> <i><a href="AT91M55800A_h.html#AT91C_DAC1_SR">AT91C_DAC1_SR</a></i> 0xFFFA8010</font><font size="-2"><li><b>DAC0</b> <i><a href="AT91M55800A_h.html#AT91C_DAC0_SR">AT91C_DAC0_SR</a></i> 0xFFFB4010</font></null></ul><br>0 = Data has been written to the Data Holding Register and not yet transferred to the Data Output Register.<br>1 = The last data written in the Data Holding Register has been transferred to the Data Output Register.<br>This is equal to 0 when the Timer Trigger is disabled or at reset. Enabling the Timer Trigger sets this bit to 1.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DAC_DATRDY"></a><b>DAC_DATRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_DATRDY">AT91C_DAC_DATRDY</a></font></td><td><b>Data Ready for Conversion</b></td></tr>
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<a name="DAC_IER"></a><h4><a href="#DAC">DAC</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> DAC_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>DAC1</b> <i><a href="AT91M55800A_h.html#AT91C_DAC1_IER">AT91C_DAC1_IER</a></i> 0xFFFA8014</font><font size="-2"><li><b>DAC0</b> <i><a href="AT91M55800A_h.html#AT91C_DAC0_IER">AT91C_DAC0_IER</a></i> 0xFFFB4014</font></null></ul><br>0 = No effect.<br>1 = Enables the Data Ready for Conversion Interrupt.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DAC_DATRDY"></a><b>DAC_DATRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_DATRDY">AT91C_DAC_DATRDY</a></font></td><td><b>Data Ready for Conversion</b></td></tr>
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<a name="DAC_IDR"></a><h4><a href="#DAC">DAC</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> DAC_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>DAC1</b> <i><a href="AT91M55800A_h.html#AT91C_DAC1_IDR">AT91C_DAC1_IDR</a></i> 0xFFFA8018</font><font size="-2"><li><b>DAC0</b> <i><a href="AT91M55800A_h.html#AT91C_DAC0_IDR">AT91C_DAC0_IDR</a></i> 0xFFFB4018</font></null></ul><br>0 = No effect.<br>1 = Disables the Data Ready for Conversion Interrupt.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DAC_DATRDY"></a><b>DAC_DATRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_DATRDY">AT91C_DAC_DATRDY</a></font></td><td><b>Data Ready for Conversion</b></td></tr>
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<a name="DAC_IMR"></a><h4><a href="#DAC">DAC</a>: <i><a href="AT91M55800A_h.html#AT91_REG">AT91_REG</a></i> DAC_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>DAC1</b> <i><a href="AT91M55800A_h.html#AT91C_DAC1_IMR">AT91C_DAC1_IMR</a></i> 0xFFFA801C</font><font size="-2"><li><b>DAC0</b> <i><a href="AT91M55800A_h.html#AT91C_DAC0_IMR">AT91C_DAC0_IMR</a></i> 0xFFFB401C</font></null></ul><br>0 = Data Ready for Conversion Interrupt is disabled.<br>1 = Data Ready for Conversion Interrupt is enabled.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DAC_DATRDY"></a><b>DAC_DATRDY</b><font size="-2"><br><a href="AT91M55800A_h.html#AT91C_DAC_DATRDY">AT91C_DAC_DATRDY</a></font></td><td><b>Data Ready for Conversion</b></td></tr>
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