📄 at91m55800a_inc.h
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#define AT91C_EBI_PAGES (0x3 << 7) // (EBI) Pages Size
#define AT91C_EBI_PAGES_1M (0x0 << 7) // (EBI) 1M Byte
#define AT91C_EBI_PAGES_4M (0x1 << 7) // (EBI) 4M Byte
#define AT91C_EBI_PAGES_16M (0x2 << 7) // (EBI) 16M Byte
#define AT91C_EBI_PAGES_64M (0x3 << 7) // (EBI) 64M Byte
#define AT91C_EBI_TDF (0x7 << 9) // (EBI) Data Float Output Time
#define AT91C_EBI_TDF_0 (0x0 << 9) // (EBI) 1 TDF
#define AT91C_EBI_TDF_1 (0x1 << 9) // (EBI) 2 TDF
#define AT91C_EBI_TDF_2 (0x2 << 9) // (EBI) 3 TDF
#define AT91C_EBI_TDF_3 (0x3 << 9) // (EBI) 4 TDF
#define AT91C_EBI_TDF_4 (0x4 << 9) // (EBI) 5 TDF
#define AT91C_EBI_TDF_5 (0x5 << 9) // (EBI) 6 TDF
#define AT91C_EBI_TDF_6 (0x6 << 9) // (EBI) 7 TDF
#define AT91C_EBI_TDF_7 (0x7 << 9) // (EBI) 8 TDF
#define AT91C_EBI_BAT (0x1 << 12) // (EBI) Byte Access Type
#define AT91C_EBI_CSEN (0x1 << 13) // (EBI) Chip Select Enable
#define AT91C_EBI_BA (0xFFF << 20) // (EBI) Base Address
// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
#define AT91C_EBI_RCB (0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
#define AT91C_EBI_ALE (0x7 << 0) // (EBI) Address Line Enable
#define AT91C_EBI_ALE_16M (0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
#define AT91C_EBI_ALE_8M (0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
#define AT91C_EBI_ALE_4M (0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
#define AT91C_EBI_ALE_2M (0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
#define AT91C_EBI_ALE_1M (0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
#define AT91C_EBI_DRP (0x1 << 4) // (EBI)
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91M55800A
// *****************************************************************************
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector egister
#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode egister
#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command egister
// ========== Register definition for WD peripheral ==========
#define AT91C_WD_SR (0xFFFF800C) // (WD) Status Register
#define AT91C_WD_CMR (0xFFFF8004) // (WD) Clock Mode Register
#define AT91C_WD_CR (0xFFFF8008) // (WD) Control Register
#define AT91C_WD_OMR (0xFFFF8000) // (WD) Overflow Mode Register
// ========== Register definition for APMC peripheral ==========
#define AT91C_APMC_SR (0xFFFF4030) // (APMC) Status Register
#define AT91C_APMC_PCR (0xFFFF4028) // (APMC) Power Control Register
#define AT91C_APMC_CGMR (0xFFFF4020) // (APMC) Clock Generator Mode Register
#define AT91C_APMC_PCSR (0xFFFF4018) // (APMC) Peripheral Clock Status Register
#define AT91C_APMC_IMR (0xFFFF403C) // (APMC) Interrupt Mask Register
#define AT91C_APMC_IER (0xFFFF4034) // (APMC) Interrupt Enable Register
#define AT91C_APMC_PMR (0xFFFF402C) // (APMC) Power Mode Register
#define AT91C_APMC_SCER (0xFFFF4000) // (APMC) System Clock Enable Register
#define AT91C_APMC_SCSR (0xFFFF4008) // (APMC) System Clock Status Register
#define AT91C_APMC_PCER (0xFFFF4010) // (APMC) Peripheral Clock Enable Register
#define AT91C_APMC_SCDR (0xFFFF4004) // (APMC) System Clock Disable Register
#define AT91C_APMC_PCDR (0xFFFF4014) // (APMC) Peripheral Clock Disable Register
#define AT91C_APMC_IDR (0xFFFF4038) // (APMC) Interrupt Disable Register
// ========== Register definition for RTC peripheral ==========
#define AT91C_RTC_IMR (0xFFFB8028) // (RTC) Interrupt Mask Register
#define AT91C_RTC_IER (0xFFFB8020) // (RTC) Interrupt Enable Register
#define AT91C_RTC_SR (0xFFFB8018) // (RTC) Status Register
#define AT91C_RTC_TAR (0xFFFB8010) // (RTC) Time Alarm Register
#define AT91C_RTC_TIMR (0xFFFB8008) // (RTC) Time Register
#define AT91C_RTC_MR (0xFFFB8000) // (RTC) Mode Register
#define AT91C_RTC_VER (0xFFFB802C) // (RTC) Valid Entry Register
#define AT91C_RTC_IDR (0xFFFB8024) // (RTC) Interrupt Disable Register
#define AT91C_RTC_SCR (0xFFFB801C) // (RTC) Status Clear Register
#define AT91C_RTC_CAR (0xFFFB8014) // (RTC) Calendar Alarm Register
#define AT91C_RTC_CALR (0xFFFB800C) // (RTC) Calendar Register
#define AT91C_RTC_HMR (0xFFFB8004) // (RTC) Hour Mode Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_MDSR (0xFFFF0058) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFSR (0xFFFF0028) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_IFER (0xFFFF0020) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_OSR (0xFFFF0018) // (PIOB) Output Status Register
#define AT91C_PIOB_OER (0xFFFF0010) // (PIOB) Output Enable Register
#define AT91C_PIOB_PSR (0xFFFF0008) // (PIOB) PIO Status Register
#define AT91C_PIOB_PDSR (0xFFFF003C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_CODR (0xFFFF0034) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_IFDR (0xFFFF0024) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_MDER (0xFFFF0050) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_IMR (0xFFFF0048) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_IER (0xFFFF0040) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_ODSR (0xFFFF0038) // (PIOB) Output Data Status Register
#define AT91C_PIOB_SODR (0xFFFF0030) // (PIOB) Set Output Data Register
#define AT91C_PIOB_PER (0xFFFF0000) // (PIOB) PIO Enable Register
#define AT91C_PIOB_MDDR (0xFFFF0054) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_ISR (0xFFFF004C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_IDR (0xFFFF0044) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_PDR (0xFFFF0004) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR (0xFFFF0014) // (PIOB) Output Disable Registerr
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_MDDR (0xFFFEC054) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_ISR (0xFFFEC04C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_IDR (0xFFFEC044) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_PDSR (0xFFFEC03C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_CODR (0xFFFEC034) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_PDR (0xFFFEC004) // (PIOA) PIO Disable Register
#define AT91C_PIOA_MDSR (0xFFFEC058) // (PIOA) Multi-driver Status Register
#define AT91C_PIOA_MDER (0xFFFEC050) // (PIOA) Multi-driver Enable Register
#define AT91C_PIOA_IMR (0xFFFEC048) // (PIOA) Interrupt Mask Register
#define AT91C_PIOA_OSR (0xFFFEC018) // (PIOA) Output Status Register
#define AT91C_PIOA_OER (0xFFFEC010) // (PIOA) Output Enable Register
#define AT91C_PIOA_PSR (0xFFFEC008) // (PIOA) PIO Status Register
#define AT91C_PIOA_PER (0xFFFEC000) // (PIOA) PIO Enable Register
#define AT91C_PIOA_IFDR (0xFFFEC024) // (PIOA) Input Filter Disable Register
#define AT91C_PIOA_ODR (0xFFFEC014) // (PIOA) Output Disable Registerr
#define AT91C_PIOA_IER (0xFFFEC040) // (PIOA) Interrupt Enable Register
#define AT91C_PIOA_ODSR (0xFFFEC038) // (PIOA) Output Data Status Register
#define AT91C_PIOA_SODR (0xFFFEC030) // (PIOA) Set Output Data Register
#define AT91C_PIOA_IFSR (0xFFFEC028) // (PIOA) Input Filter Status Register
#define AT91C_PIOA_IFER (0xFFFEC020) // (PIOA) Input Filter Enable Register
// ========== Register definition for TC5 peripheral ==========
#define AT91C_TC5_IDR (0xFFFD40A8) // (TC5) Interrupt Disable Register
#define AT91C_TC5_SR (0xFFFD40A0) // (TC5) Status Register
#define AT91C_TC5_RB (0xFFFD4098) // (TC5) Register B
#define AT91C_TC5_CV (0xFFFD4090) // (TC5) Counter Value
#define AT91C_TC5_CCR (0xFFFD4080) // (TC5) Channel Control Register
#define AT91C_TC5_IMR (0xFFFD40AC) // (TC5) Interrupt Mask Register
#define AT91C_TC5_IER (0xFFFD40A4) // (TC5) Interrupt Enable Register
#define AT91C_TC5_RC (0xFFFD409C) // (TC5) Register C
#define AT91C_TC5_RA (0xFFFD4094) // (TC5) Register A
#define AT91C_TC5_CMR (0xFFFD4084) // (TC5) Channel Mode Register
// ========== Register definition for TC4 peripheral ==========
#define AT91C_TC4_IDR (0xFFFD4068) // (TC4) Interrupt Disable Register
#define AT91C_TC4_SR (0xFFFD4060) // (TC4) Status Register
#define AT91C_TC4_RB (0xFFFD4058) // (TC4) Register B
#define AT91C_TC4_CV (0xFFFD4050) // (TC4) Counter Value
#define AT91C_TC4_CCR (0xFFFD4040) // (TC4) Channel Control Register
#define AT91C_TC4_IMR (0xFFFD406C) // (TC4) Interrupt Mask Register
#define AT91C_TC4_IER (0xFFFD4064) // (TC4) Interrupt Enable Register
#define AT91C_TC4_RC (0xFFFD405C) // (TC4) Register C
#define AT91C_TC4_RA (0xFFFD4054) // (TC4) Register A
#define AT91C_TC4_CMR (0xFFFD4044) // (TC4) Channel Mode Register
// ========== Register definition for TC3 peripheral ==========
#define AT91C_TC3_RA (0xFFFD4014) // (TC3) Register A
#define AT91C_TC3_CMR (0xFFFD4004) // (TC3) Channel Mode Register
#define AT91C_TC3_IDR (0xFFFD4028) // (TC3) Interrupt Disable Register
#define AT91C_TC3_SR (0xFFFD4020) // (TC3) Status Register
#define AT91C_TC3_RB (0xFFFD4018) // (TC3) Register B
#define AT91C_TC3_CV (0xFFFD4010) // (TC3) Counter Value
#define AT91C_TC3_CCR (0xFFFD4000) // (TC3) Channel Control Register
#define AT91C_TC3_IMR (0xFFFD402C) // (TC3) Interrupt Mask Register
#define AT91C_TC3_IER (0xFFFD4024) // (TC3) Interrupt Enable Register
#define AT91C_TC3_RC (0xFFFD401C) // (TC3) Register C
// ========== Register definition for TCB1 peripheral ==========
#define AT91C_TCB1_BCR (0xFFFD40C0) // (TCB1) TC Block Control Register
#define AT91C_TCB1_BMR (0xFFFD40C4) // (TCB1) TC Block Mode Register
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IDR (0xFFFD00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR (0xFFFD00A0) // (TC2) Status Register
#define AT91C_TC2_RB (0xFFFD0098) // (TC2) Register B
#define AT91C_TC2_CV (0xFFFD0090) // (TC2) Counter Value
#define AT91C_TC2_CCR (0xFFFD0080) // (TC2) Channel Control Register
#define AT91C_TC2_IMR (0xFFFD00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER (0xFFFD00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC (0xFFFD009C) // (TC2) Register C
#define AT91C_TC2_RA (0xFFFD0094) // (TC2) Register A
#define AT91C_TC2_CMR (0xFFFD0084) // (TC2) Channel Mode Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IMR (0xFFFD006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER (0xFFFD0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC (0xFFFD005C) // (TC1) Register C
#define AT91C_TC1_RA (0xFFFD0054) // (TC1) Register A
#define AT91C_TC1_CMR (0xFFFD0044) // (TC1) Channel Mode Register
#define AT91C_TC1_IDR (0xFFFD0068) // (TC1) Inte⌨️ 快捷键说明
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