at91m55800a_inc.h

AT91M5800a例子

#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate
#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
// *****************************************************************************
// *** Register offset in AT91S_ADC structure ***
#define ADC_CR          ( 0) // Control Register
#define ADC_MR          ( 4) // Mode Register
#define ADC_CHER        (16) // Channel Enable Register
#define ADC_CHDR        (20) // Channel Disable Register
#define ADC_CHSR        (24) // Channel Status Register
#define ADC_SR          (32) // Status Register
#define ADC_IER         (36) // Interrupt Enable Register
#define ADC_IDR         (40) // Interrupt Disable Register
#define ADC_IMR         (44) // Interrupt Mask Register
#define ADC_CDR         (48) // Convert Data Register
// -------- ADC_CR : (ADC Offset: 0x0) Control Register -------- 
#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
// -------- ADC_MR : (ADC Offset: 0x4) Mode Register -------- 
#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
#define AT91C_ADC_TRG             (0x7 <<  1) // (ADC) Trigger Selection
#define 	AT91C_ADC_TRG_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
#define 	AT91C_ADC_TRG_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
#define 	AT91C_ADC_TRG_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
#define 	AT91C_ADC_TRG_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
#define 	AT91C_ADC_TRG_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
#define 	AT91C_ADC_TRG_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
#define 	AT91C_ADC_TRG_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
#define AT91C_ADC_RES             (0x1 <<  4) // (ADC) Resolution.
#define 	AT91C_ADC_RES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
#define 	AT91C_ADC_RES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
#define AT91C_ADC_PRESCAL         (0x1F <<  8) // (ADC) Prescaler rate selection
// -------- 	ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- 
#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
// -------- 	ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- 
// -------- 	ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- 
// -------- ADC_SR : (ADC Offset: 0x20) Status Register -------- 
#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
// -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- 
// -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- 
// -------- ADC_IMR : (ADC Offset: 0x2c) Interrupt Mask Register -------- 
// -------- ADC_CDR : (ADC Offset: 0x30) Convert Data Register -------- 
#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Digital to Analog Convertor
// *****************************************************************************
// *** Register offset in AT91S_DAC structure ***
#define DAC_CR          ( 0) // Control Register
#define DAC_MR          ( 4) // Mode Register
#define DAC_DHR         ( 8) // Data Holding Register
#define DAC_DOR         (12) // Data Output Register
#define DAC_SR          (16) // Status Register
#define DAC_IER         (20) // Interrupt Enable Register
#define DAC_IDR         (24) // Interrupt Disable Register
#define DAC_IMR         (28) // Interrupt Mask Register
// -------- DAC_CR : (DAC Offset: 0x0) Control Register -------- 
#define AT91C_DAC_SWRST           (0x1 <<  0) // (DAC) Software Reset
// -------- DAC_MR : (DAC Offset: 0x4) Mode Register -------- 
#define AT91C_DAC_TTRGEN          (0x1 <<  0) // (DAC) Timer Trigger Enable
#define 	AT91C_DAC_TTRGEN_DIS                  (0x0) // (DAC) The data written into the Data Holding Register (DAC_DHR) is transferred one main clock cycle later to the data output register (DAC_DOR).
#define 	AT91C_DAC_TTRGEN_EN                   (0x1) // (DAC) The data transfer from the DAC_DHR to the DAC_DOR is synchronized by the timer trigger.
#define AT91C_DAC_TTRGSEL         (0x7 <<  1) // (DAC) Timer Trigger Selection
#define 	AT91C_DAC_TTRGSEL_TIOA0                (0x0 <<  1) // (DAC) Selected TRGSEL = TIAO0
#define 	AT91C_DAC_TTRGSEL_TIOA1                (0x1 <<  1) // (DAC) Selected TRGSEL = TIAO1
#define 	AT91C_DAC_TTRGSEL_TIOA2                (0x2 <<  1) // (DAC) Selected TRGSEL = TIAO2
#define 	AT91C_DAC_TTRGSEL_TIOA3                (0x3 <<  1) // (DAC) Selected TRGSEL = TIAO3
#define 	AT91C_DAC_TTRGSEL_TIOA4                (0x4 <<  1) // (DAC) Selected TRGSEL = TIAO4
#define 	AT91C_DAC_TTRGSEL_TIOA5                (0x5 <<  1) // (DAC) Selected TRGSEL = TIAO5
#define AT91C_DAC_RES             (0x1 <<  4) // (DAC) Resolution.
#define 	AT91C_DAC_RES_10_BIT               (0x0 <<  4) // (DAC) 10-bit resolution
#define 	AT91C_DAC_RES_8_BIT                (0x1 <<  4) // (DAC) 8-bit resolution
// -------- DAC_DHR : (DAC Offset: 0x8) Data Holding Register -------- 
#define AT91C_DAC_DATA            (0x3FF <<  0) // (DAC) Data to be Converted
// -------- DAC_DOR : (DAC Offset: 0xc) Data Output Register -------- 
// -------- DAC_SR : (DAC Offset: 0x10) Status Register -------- 
#define AT91C_DAC_DATRDY          (0x1 <<  0) // (DAC) Data Ready for Conversion
// -------- DAC_IER : (DAC Offset: 0x14) Data Ready for Conversion Interrupt Enable -------- 
// -------- DAC_IDR : (DAC Offset: 0x18) Data Ready for Conversion Interrupt Disable -------- 
// -------- DAC_IMR : (DAC Offset: 0x1c) Data Ready for Conversion Interrupt Mask -------- 

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Special Function Interface
// *****************************************************************************
// *** Register offset in AT91S_SF structure ***
#define SF_CIDR         ( 0) // Chip ID Register
#define SF_EXID         ( 4) // Chip ID Extension Register
#define SF_RSR          ( 8) // Reset Status Register
#define SF_PMR          (24) // Protect Mode Register
// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register -------- 
#define AT91C_SF_VERSION          (0x1F <<  0) // (SF) Version of the chip
#define AT91C_SF_BIT5             (0x1 <<  5) // (SF) Hardwired at 0
#define AT91C_SF_BIT6             (0x1 <<  6) // (SF) Hardwired at 1
#define AT91C_SF_BIT7             (0x1 <<  7) // (SF) Hardwired at 0
#define AT91C_SF_NVPSIZ           (0xF <<  8) // (SF) Nonvolatile Program Memory Size
#define 	AT91C_SF_NVPSIZ_NONE                 (0x0 <<  8) // (SF) None
#define 	AT91C_SF_NVPSIZ_32K                  (0x3 <<  8) // (SF) 32K Bytes
#define 	AT91C_SF_NVPSIZ_64K                  (0x5 <<  8) // (SF) 64K Bytes
#define 	AT91C_SF_NVPSIZ_128K                 (0x7 <<  8) // (SF) 128K Bytes
#define 	AT91C_SF_NVPSIZ_256K                 (0x11 <<  8) // (SF) 256K Bytes
#define AT91C_SF_NVDSIZ           (0xF << 12) // (SF) Nonvolatile Data Memory Size
#define 	AT91C_SF_NVDSIZ_NONE                 (0x0 << 12) // (SF) None
#define AT91C_SF_VDSIZ            (0xF << 16) // (SF) Volatile Data Memory Size
#define 	AT91C_SF_VDSIZ_NONE                 (0x0 << 16) // (SF) None
#define 	AT91C_SF_VDSIZ_1K                   (0x3 << 16) // (SF) 1K Bytes
#define 	AT91C_SF_VDSIZ_2K                   (0x5 << 16) // (SF) 2K Bytes
#define 	AT91C_SF_VDSIZ_4K                   (0x7 << 16) // (SF) 4K Bytes
#define 	AT91C_SF_VDSIZ_8K                   (0x11 << 16) // (SF) 8K Bytes
#define AT91C_SF_ARCH             (0xFF << 20) // (SF) Chip Architecture
#define 	AT91C_SF_ARCH_AT91x40              (0x28 << 20) // (SF) AT91x40yyy
#define 	AT91C_SF_ARCH_AT91x55              (0x37 << 20) // (SF) AT91x55yyy
#define 	AT91C_SF_ARCH_AT91x63              (0x3F << 20) // (SF) AT91x63yyy
#define AT91C_SF_NVPTYP           (0x7 << 28) // (SF) Nonvolatile Program Memory Type
#define 	AT91C_SF_NVPTYP_NVPTYP_M             (0x1 << 28) // (SF) 'M' Series or 'F' Series
#define 	AT91C_SF_NVPTYP_NVPTYP_R             (0x4 << 28) // (SF) 'R' Series
#define AT91C_SF_EXT              (0x1 << 31) // (SF) Extension Flag
// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information -------- 
#define AT91C_SF_RESET            (0xFF <<  0) // (SF) Cause of Reset
#define 	AT91C_SF_RESET_WD                   (0x35) // (SF) Internal Watchdog
#define 	AT91C_SF_RESET_EXT                  (0x6C) // (SF) External Pin
// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register -------- 
#define AT91C_SF_AIC              (0x1 <<  5) // (SF) AIC Protect Mode Enable
#define AT91C_SF_PMRKEY           (0xFFFF << 16) // (SF) Protect Mode Register Key

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR External Bus Interface
// *****************************************************************************
// *** Register offset in AT91S_EBI structure ***
#define EBI_CSR         ( 0) // Chip-select Register
#define EBI_RCR         (32) // Remap Control Register
#define EBI_MCR         (36) // Memory Control Register
// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register -------- 
#define AT91C_EBI_DBW             (0x3 <<  0) // (EBI) Data Bus Width
#define 	AT91C_EBI_DBW_16                   (0x1) // (EBI) 16-bit data bus width
#define 	AT91C_EBI_DBW_8                    (0x2) // (EBI) 8-bit data bus width
#define AT91C_EBI_NWS             (0x7 <<  2) // (EBI) Number of wait states
#define 	AT91C_EBI_NWS_1                    (0x0 <<  2) // (EBI) 1 wait state
#define 	AT91C_EBI_NWS_2                    (0x1 <<  2) // (EBI) 2 wait state
#define 	AT91C_EBI_NWS_3                    (0x2 <<  2) // (EBI) 3 wait state
#define 	AT91C_EBI_NWS_4                    (0x3 <<  2) // (EBI) 4 wait state
#define 	AT91C_EBI_NWS_5                    (0x4 <<  2) // (EBI) 5 wait state
#define 	AT91C_EBI_NWS_6                    (0x5 <<  2) // (EBI) 6 wait state
#define 	AT91C_EBI_NWS_7                    (0x6 <<  2) // (EBI) 7 wait state
#define 	AT91C_EBI_NWS_8                    (0x7 <<  2) // (EBI) 8 wait state
#define AT91C_EBI_WSE             (0x1 <<  5) // (EBI) Wait State Enable