at91m55800a_inc.h

AT91M5800a例子

// ----------------------------------------------------------------------------
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
// ----------------------------------------------------------------------------
//  The software is delivered "AS IS" without warranty or condition of any
//  kind, either express, implied or statutory. This includes without
//  limitation any warranty or condition with respect to merchantability or
//  fitness for any particular purpose, or against the infringements of
//  intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name           : AT91M55800A.h
// Object              : AT91M55800A definitions
// Generated           : AT91 SW Application Group  02/19/2003 (10:45:02)
// 
// CVS Reference       : /AT91M55800A.pl/1.18/Thu Nov 21 13:37:56 2002//
// CVS Reference       : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//
// CVS Reference       : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//
// CVS Reference       : /APMC_55800A.pl/1.1/Thu Nov 21 13:37:30 2002//
// CVS Reference       : /RTC_1366C.pl/1.2/Mon Nov 04 17:51:00 2002//
// CVS Reference       : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//
// CVS Reference       : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//
// CVS Reference       : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//
// CVS Reference       : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//
// CVS Reference       : /SPI_1244C.pl/1.5/Tue Nov 05 17:13:48 2002//
// CVS Reference       : /ADC_55800A.pl/1.3/Tue Nov 05 17:02:04 2002//
// CVS Reference       : /DAC_55800A.pl/1.1/Tue Nov 05 12:43:10 2002//
// CVS Reference       : /SF_M55800A.pl/1.1/Tue Nov 05 15:45:40 2002//
// CVS Reference       : /EBI_55800A.pl/1.3/Wed Feb 19 09:25:22 2003//
// ----------------------------------------------------------------------------

// Hardware register definition

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR         ( 0) // Source Mode egister
#define AIC_SVR         (128) // Source Vector egister
#define AIC_IVR         (256) // IRQ Vector Register
#define AIC_FVR         (260) // FIQ Vector Register
#define AIC_ISR         (264) // Interrupt Status Register
#define AIC_IPR         (268) // Interrupt Pending Register
#define AIC_IMR         (272) // Interrupt Mask Register
#define AIC_CISR        (276) // Core Interrupt Status Register
#define AIC_IECR        (288) // Interrupt Enable Command Register
#define AIC_IDCR        (292) // Interrupt Disable Command egister
#define AIC_ICCR        (296) // Interrupt Clear Command Register
#define AIC_ISCR        (300) // Interrupt Set Command Register
#define AIC_EOICR       (304) // End of Interrupt Command Register
#define AIC_SPU         (308) // Spurious Vector Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Watchdog Timer Interface
// *****************************************************************************
// *** Register offset in AT91S_WD structure ***
#define WD_OMR          ( 0) // Overflow Mode Register
#define WD_CMR          ( 4) // Clock Mode Register
#define WD_CR           ( 8) // Control Register
#define WD_SR           (12) // Status Register
// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- 
#define AT91C_WD_WDEN             (0x1 <<  0) // (WD) Watchdog Enable
#define AT91C_WD_RSTEN            (0x1 <<  1) // (WD) Reset Enable
#define AT91C_WD_IRQEN            (0x1 <<  2) // (WD) Interrupt Enable
#define AT91C_WD_EXTEN            (0x1 <<  3) // (WD) External Signal Enable
#define AT91C_WD_OKEY             (0xFFF <<  4) // (WD) Watchdog Enable
// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- 
#define AT91C_WD_WDCLKS           (0x3 <<  0) // (WD) Clock Selection
#define 	AT91C_WD_WDCLKS_MCK32                (0x0) // (WD) Master Clock divided by 32
#define 	AT91C_WD_WDCLKS_MCK128               (0x1) // (WD) Master Clock divided by 128
#define 	AT91C_WD_WDCLKS_MCK1024              (0x2) // (WD) Master Clock divided by 1024
#define 	AT91C_WD_WDCLKS_MCK4096              (0x3) // (WD) Master Clock divided by 4096
#define AT91C_WD_HPCV             (0xF <<  2) // (WD) High Pre-load Counter Value
#define AT91C_WD_CKEY             (0x1FF <<  7) // (WD) Clock Access Key
// -------- WD_CR : (WD Offset: 0x8) Control Register -------- 
#define AT91C_WD_RSTKEY           (0xFFFF <<  0) // (WD) Restart Key
// -------- WD_SR : (WD Offset: 0xc) Status Register -------- 
#define AT91C_WD_WDOVF            (0x1 <<  0) // (WD) Watchdog Overflow

// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Advanced Power Management Controler
// *****************************************************************************
// *** Register offset in AT91S_APMC structure ***
#define APMC_SCER       ( 0) // System Clock Enable Register
#define APMC_SCDR       ( 4) // System Clock Disable Register
#define APMC_SCSR       ( 8) // System Clock Status Register
#define APMC_PCER       (16) // Peripheral Clock Enable Register
#define APMC_PCDR       (20) // Peripheral Clock Disable Register
#define APMC_PCSR       (24) // Peripheral Clock Status Register
#define APMC_CGMR       (32) // Clock Generator Mode Register
#define APMC_PCR        (40) // Power Control Register
#define APMC_PMR        (44) // Power Mode Register
#define APMC_SR         (48) // Status Register
#define APMC_IER        (52) // Interrupt Enable Register
#define APMC_IDR        (56) // Interrupt Disable Register
#define APMC_IMR        (60) // Interrupt Mask Register
// -------- APMC_SCER : (APMC Offset: 0x0) System Clock Enable Register -------- 
#define AT91C_APMC_CPU            (0x1 <<  0) // (APMC) System Clock
// -------- APMC_SCDR : (APMC Offset: 0x4) System Clock Disable Register -------- 
// -------- APMC_SCSR : (APMC Offset: 0x8) System Clock Status Register -------- 
// -------- APMC_PCER : (APMC Offset: 0x10) Peripheral Clock Enable Register -------- 
#define AT91C_APMC_US0            (0x1 <<  2) // (APMC) Usart 0 Clock
#define AT91C_APMC_US1            (0x1 <<  3) // (APMC) Usart 1 Clock
#define AT91C_APMC_US2            (0x1 <<  4) // (APMC) Usart 2 Clock
#define AT91C_APMC_SPI            (0x1 <<  5) // (APMC) Serial Peripheral Interface Clock
#define AT91C_APMC_TC0            (0x1 <<  6) // (APMC) Timer Counter 0 Clock
#define AT91C_APMC_TC1            (0x1 <<  7) // (APMC) Timer Counter 1 Clock
#define AT91C_APMC_TC2            (0x1 <<  8) // (APMC) Timer Counter 2 Clock
#define AT91C_APMC_TC3            (0x1 <<  9) // (APMC) Timer Counter 3 Clock
#define AT91C_APMC_TC4            (0x1 << 10) // (APMC) Timer Counter 4 Clock
#define AT91C_APMC_TC5            (0x1 << 11) // (APMC) Timer Counter 5 Clock
#define AT91C_APMC_PIOA           (0x1 << 13) // (APMC) PIOA  Clock
#define AT91C_APMC_PIOB           (0x1 << 14) // (APMC) PIOB Clock
#define AT91C_APMC_ADC0           (0x1 << 15) // (APMC) Analog to Digital Converter 0 Clock
#define AT91C_APMC_ADC1           (0x1 << 16) // (APMC) Analog to Digital Converter 1 Clock
#define AT91C_APMC_DAC0           (0x1 << 17) // (APMC) Digital to Analog Converter 0 Clock
#define AT91C_APMC_DAC1           (0x1 << 18) // (APMC) Digital to Analog Converter 1 Clock
// -------- APMC_PCDR : (APMC Offset: 0x14) Peripheral Clock Disable Register -------- 
// -------- APMC_PCSR : (APMC Offset: 0x18) Peripheral Clock Satus Register -------- 
// -------- APMC_CGMR : (APMC Offset: 0x20) Clock Generator Mode Register -------- 
#define AT91C_APMC_MOSCBYP        (0x1 <<  0) // (APMC) Main Oscillator Bypass
#define AT91C_APMC_MOSCEN         (0x1 <<  1) // (APMC) Main Oscillator Enable
#define AT91C_APMC_MCKODS         (0x1 <<  2) // (APMC) Master Clock Output Disable
#define AT91C_APMC_PRES           (0x7 <<  4) // (APMC) Prescaler Selection
#define 	AT91C_APMC_PRES_NONE                 (0x0 <<  4) // (APMC) Prescaler Output is the selected clock
#define 	AT91C_APMC_PRES_DIV2                 (0x1 <<  4) // (APMC) Selected clock is divided by 2
#define 	AT91C_APMC_PRES_DIV4                 (0x2 <<  4) // (APMC) Selected clock is divided by 4
#define 	AT91C_APMC_PRES_DIV8                 (0x3 <<  4) // (APMC) Selected clock is divided by 8
#define 	AT91C_APMC_PRES_DIV16                (0x4 <<  4) // (APMC) Selected clock is divided by 16
#define 	AT91C_APMC_PRES_DIV32                (0x5 <<  4) // (APMC) Selected clock is divided by 32
#define 	AT91C_APMC_PRES_DIV64                (0x6 <<  4) // (APMC) Selected clock is divided by 64
#define AT91C_APMC_MUL            (0x3F <<  8) // (APMC) Phase Lock Loop Factor
#define AT91C_APMC_CSS            (0x3 << 14) // (APMC) Clock Source Selection
#define 	AT91C_APMC_CSS_LF                   (0x0 << 14) // (APMC) Low-frequency clock provided by the RTC
#define 	AT91C_APMC_CSS_MOSC                 (0x1 << 14) // (APMC) Main Oscillator Output or external clock
#define 	AT91C_APMC_CSS_PLL                  (0x2 << 14) // (APMC) Phase Locked Loop Output
#define AT91C_APMC_OSCOUNT        (0x3F << 16) // (APMC) Main Oscillator Counter
#define AT91C_APMC_PLLCOUNT       (0x1 << 24) // (APMC) PLL Lock Counter
// -------- APMC_PCR : (APMC Offset: 0x28) Power Control Register -------- 
#define AT91C_APMC_SHDALC         (0x1 <<  0) // (APMC) Shut-down or Alarm Command
#define AT91C_APMC_WKACKC         (0x1 <<  1) // (APMC) Wake-up or Alarm Acknoledge Command
// -------- APMC_PMR : (APMC Offset: 0x2c) Power Mode Register -------- 
#define AT91C_APMC_SHDALS         (0x3 <<  0) // (APMC) Shut-down or Alarm Command
#define 	AT91C_APMC_SHDALS_OUT_TRIS             (0x0) // (APMC) Tri-stated
#define 	AT91C_APMC_SHDALS_OUT_LEVEL0           (0x1) // (APMC) Level 0
#define 	AT91C_APMC_SHDALS_OUT_LEVEL1           (0x2) // (APMC) Level 1
#define AT91C_APMC_WKACKS         (0x1 <<  2) // (APMC) Wake-up or Alarm Acknoledge Command
#define 	AT91C_APMC_WKACKS_OUT_TRIS             (0x0 <<  2) // (APMC) Tri-stated
#define 	AT91C_APMC_WKACKS_OUT_LEVEL0           (0x1 <<  2) // (APMC) Level 0
#define 	AT91C_APMC_WKACKS_OUT_LEVEL1           (0x2 <<  2) // (APMC) Level 1
#define AT91C_APMC_ALWKEN         (0x1 <<  4) // (APMC) Alarm Wake-up Enable
#define AT91C_APMC_WKEDG          (0x3 <<  6) // (APMC) Wake-up Input Edge Selection
#define 	AT91C_APMC_WKEDG_NONE                 (0x0 <<  6) // (APMC) None. No edge is detected on wake-up
#define 	AT91C_APMC_WKEDG_POS_EDG              (0x1 <<  6) // (APMC) Positive edge
#define 	AT91C_APMC_WKEDG_NEG_EDG              (0x2 <<  6) // (APMC) Negative edge
#define 	AT91C_APMC_WKEDG_BOTH_EDG             (0x3 <<  6) // (APMC) Both edges 
// -------- APMC_SR : (APMC Offset: 0x30) APMC Status Register -------- 
#define AT91C_APMC_MOSCS          (0x1 <<  0) // (APMC) Main Oscillator Status
#define AT91C_APMC_LOCK           (0x1 <<  1) // (APMC) PLL Lock Status
// -------- APMC_IER : (APMC Offset: 0x34) APMC Interrupt Enable Register -------- 
// -------- APMC_IDR : (APMC Offset: 0x38) APMC Interrupt Disable Register -------- 
// -------- APMC_IMR : (APMC Offset: 0x3c) APMC Interrupt Mask Register -------- 

// *****************************************************************************