syslib.c

4510b的vxworks的BSP

/* sysLib.c - Samsung SNDS100 system-dependent routines */

#include "copyright_wrs.h"

/*
modification history
--------------------
01b,25nov99,knp changed name "end" to "secEnd"
01a,26aug99,ak/knp adapted for Samsung's snds100 board
*/

/*
DESCRIPTION
This library provides board-specific routines for the Samsung SNDS100
Ver 1.0 Development Board BSP.

It #includes the following chip drivers:
    nullVme.c -         dummy VMEbus routines
    sndsTimer.c -       SNDS timer driver
    sndsIntrCtl.c -     SNDS interrupt controller driver
    nullNvRam.c -	dummy NVRAM routines

It #includes the following BSP files:
    sysSerial.c -	serial device initialisation routines
    sysEnd.c -		END network driver support routines.

INCLUDE FILES: sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h

SEE ALSO:
.pG "Configuration"
.I "ARM Architecture Reference Manual,"
.I "Samsung KS32C50100 Microcontroller User's Manual,"
.I "Samsung KS32C5000(A)/50100 Microcontroller Application Notes."
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#if (CPU == ARM710A)
#include "cacheLib.h"
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
#endif /* CPU == ARM710A */

/* imports */

IMPORT char end;		  /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit;	/* ptr to fn to split stack */


/* globals */

#if (CPU == ARM710A)
/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC or INCLUDE_MMU_FULL are
 * defined.
 *
 * Clearly, this structure is only needed if the CPU has an MMU!
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    /* adrs and length parameters must be page-aligned (multiples of 0x1000) */
	
    /* DRAM */
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,	/* virtual address */
    (void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */
    ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
    },

    /*
     * ROM is normally marked as uncacheable by VxWorks. We leave it like that
     * for the time being, even though this has a severe impact on execution
     * speed from ROM.
     */
    {
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
#ifdef INCLUDE_FLASH
    /* needs to be writable */

    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
#else
    VM_STATE_VALID	| VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
#endif
    },

    /*
     * I/O space:
     * Do not map in all I/O space, only that which has something there.
     * Otherwise we will use all of RAM allocating page tables!
     */
#ifdef INCLUDE_SERIAL
    {
    (void *) SERIAL_A_BASE_ADR,	/* KS32C50100 DUART */
    (void *) SERIAL_B_BASE_ADR,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
  	  VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif /* INCLUDE_SERIAL */
    {
    (void *) ASIC_BASE,		/* Interrupt controller */
    (void *) ASIC_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    (void *) SNDS_TIMER_BASE,	/* Counter/Timer */
    (void *) SNDS_TIMER_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#ifdef INCLUDE_OLI_END
    /* PCMCIA address areas */
    {
    (void *) NISA_BASE,		/* PCMCIA I/O space */
    (void *) NISA_BASE,
    PAGE_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
    {
    (void *) NISA_PCMEM,	/* PCMCIA memory (and attribute memory */
    (void *) NISA_PCMEM,
    0x24000,			/*
				 * (64 kB memory + (4 kB attribute memory for
				 * each of two slots) ) * 2 because it is
				 * sparsely-addressed.
				 */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },
#endif	/* INCLUDE_OLI_END */
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
#endif /* CPU == ARM710A */

int	sysBus	     = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	     = CPU;		/* system cpu type */
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* proc	essor number of this cpu */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


/* locals */


#if SNDS_INT_NUM_LEVELS != 21
#   error sndsIntLvlMask is wrong size for number of levels
#endif


/* defines */

	
/* externals */

IMPORT void   sndsIntDevInit (void);
IMPORT void   sysIntStackSplit (char *, long);

/*local defines*/
#ifndef SNDS_CTRL_REG_READ
#   define SNDS_CTRL_REG_READ(x,result) \
	    ((result) = *(volatile UINT32 *)(x))
#endif	/*SNDS_READ*/

#ifndef SNDS_CTRL_REG_WRITE
#   define SNDS_CTRL_REG_WRITE(x,data) \
	    (*((volatile UINT32 *)(x)) = (data))
#endif /*SNDS_WRITE*/



/* globals */


/* forward LOCAL functions declarations */


/* forward declarations */

char *	sysPhysMemTop (void);
void sndsCacheFlush(void);  
void sndsCacheEnable(int cachesize);
void sndsCacheDisable(void);

/* included source files */

#ifdef INCLUDE_FLASH
#include "nvRamToFlash.c"
#include "mem/flashMem.c"
#endif  /* INCLUDE_FLASH */

#include "vme/nullVme.c"
#include "sysSerial.c"
#include "sndsIIC.c"
#include "sndsSio.c"
#include "sndsTimer.c"
#include "sndsIntrCtl.c"
#include "sysEnd.c"
/*******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
* 
* RETURNS: A pointer to a string identifying the board and CPU.
*/

char *sysModel (void)
    {
#if	(CPU == ARM7TDMI_T)
    return	"ARM PID - ARM7TDMI (Thumb)";
#elif	(CPU == ARM7TDMI)
    return	"KS32C50100 FOR SNDS100 Ver 1.0";
#elif	(CPU == ARM710A)
    return	"ARM PID - ARM710A";
#endif	/* (CPU == ARM7TDMI_T) */
    }

/*******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.1/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.1/<x>. BSP_REV is concatanated to BSP_VERSION to form the
* BSP identification string.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/*******************************************************************************
*
* sysHwInit - initialize the CPU board hardware
*
* This routine initializes various features of the hardware.
* Normally, it is called from usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    /* install the IRQ/SVC interrupt stack splitting routine */

    _func_armIntStackSplit = sysIntStackSplit;

#ifdef  INCLUDE_CACHE_SUPPORT
    sndsCacheEnable(SNDS_CACHE_8K);		/* enable  cache */
#endif	/* INCLUDE_CACHE_ENABLE */

    sysSerialHwInit ();      /* initialise serial data structure */
	sndsIICDevInit();
    }

/*******************************************************************************
*
* sysHwInit2 - additional system configuration and initialization
*
* This routine connects system interrupts and does any additional
* configuration necessary.
*
* RETURNS: N/A
*
* NOMANUAL
*
* Note: this is called from sysClkConnect() in the timer driver.
*/

void sysHwInit2 (void)
    {
    /* initialise the interrupt library and interrupt driver */

    intLibInit (SNDS_INT_NUM_LEVELS, SNDS_INT_NUM_LEVELS, INT_MODE);
    sndsIntDevInit();

    /* connect sys clock interrupt and auxiliary clock interrupt */

    (void)intConnect (INUM_TO_IVEC (INT_VEC_TIMER0), sysClkInt, 0);
    (void)intConnect (INUM_TO_IVEC (INT_VEC_TIMER1), sysAuxClkInt, 0);

    /* connect serial interrupt */
    sysSerialHwInit2();
	sndsIICDevInit2();
    }

/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory