snds100.h

4510b的vxworks的BSP

#define rROMCON1 	 0x60
#define rROMCON2 	 0x60
#define rROMCON3 	 0x60
#define rROMCON4 	 0x60
#define rROMCON5 	 0x60		/*ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5*/

/****************************************************************************
* -> DRAMCON0 : RAM Bank0 control register 
*/
#define EDO_Mode0 	   1 		 /*(EDO)0=Normal, 1=EDO DRAM*/
#define CasPrechargeTime0  0 		 /*(Tcp)0=1cycle,1=2cycle*/
#define CasStrobeTime0     1 		 /*(Tcs)0=1cycle ~ 3=4cycle*/
#define DRAMCON0Reserved   1 		 /* Must be set to 1*/
#define RAS2CASDelay0      0 		 /*(Trc)0=1cycle,1=2cycle*/
#define RASPrechargeTime0  2 		 /*(Trp)0=1cycle ~ 3=4clcyle*/
#define DRAMBasePtr0       (0x100<<10)  /*=0x1000000*/
#define DRAMBasePtr0_S	   0x00
#define DRAMEndPtr0  	   (0x140<<20)  /*=0x0400000 - 4 MB */
#define DRAMEndPtr0_S  	   (0x040<<20)  /*=0x0400000 - 4 MB */
#define NoColumnAddr0  	   2 		 /*0=8bit,1=9bit,2=10bit,3=11bits*/

#define Tcs0 		  (CasStrobeTime0<<1)
#define Tcp0 		  (CasPrechargeTime0<<3)
#define dumy0 		  (DRAMCON0Reserved<<4)    	/*dummy cycle*/
#define Trc0 		  (RAS2CASDelay0<<7)
#define Trp0 		  (RASPrechargeTime0<<8)
#define CAN0 		  (NoColumnAddr0<<30)

#define rDRAMCON0 	  (CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)
#define rDRAMCON0_S   (CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)

#define rDRAMCON1		0x00
#define rDRAMCON2		0x00
#define rDRAMCON3 		0x00

#define SRAS2CASDelay0 	  	1 		/*(Trc)0=1cycle,1=2cycle*/
#define SRASPrechargeTime0	3 		/*(Trp)0=1cycle ~ 3=4clcyle*/
#define SNoColumnAddr0 		0 		/*0=8bit,1=9bit,2=10bit,3=11bits*/
#define SCAN0 			(SNoColumnAddr0<<30)
#define STrc0 			(SRAS2CASDelay0<<7)
#define STrp0 			(SRASPrechargeTime0<<8)

#define rSDRAMCON0 		(SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0)
#define rSDRAMCON0_S 	(SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0)

#define rSDRAMCON1		0x00
#define rSDRAMCON2		0x00
#define rSDRAMCON3 		0x00

/**************************************************************************
* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register 
*/

#define RefCycle 		 16 		/*Unit [us], 1k refresh 16ms*/

/*RefCycle EQU 8 ;Unit [us], 1k refresh 16ms*/

#define CASSetupTime 		 0 		/*0=1cycle, 1=2cycle*/
#define CASHoldTime 		 0 		/*0=1cycle, 1=2cycle, 2=3cycle,
						*;3=4cycle, 4=5cycle,*/
#define RefCycleValue 		 ((2048+1-(RefCycle*fMCLK))<<21)
#define Tcsr 			 (CASSetupTime<<20) /* 1cycle */
#define Tcs 			 (CASHoldTime<<17)
#define ExtIOBase 		 0x18360 	/* Refresh enable, VSF=1*/

#define rREFEXTCON 		 (RefCycleValue+Tcsr+Tcs+ExtIOBase)

/******************************************************************
*SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
*/

#define SRefCycle 		 8 		/*Unit [us], 4k refresh 64ms*/
#define ROWcycleTime 		 3 		/*0=1cycle, 1=2cycle, 2=3cycle,
						3=4cycle, 4=5cycle,*/
#define SRefCycleValue 		((2048+1-(SRefCycle*fMCLK))<<21)
#define STrc 			(ROWcycleTime<<17)
#define rSREFEXTCON 	(SRefCycleValue+STrc+ExtIOBase)


#define SNDS_INT_NUM_LEVELS	21
#define SNDS_INT_CSR_MODE	SNDS_INTMODE
#define SNDS_INT_CSR_PEND	SNDS_INTPEND
#define SNDS_INT_CSR_ENB	SNDS_INTMASK
#define SNDS_INT_CSR_DIS	SNDS_INTMASK
#define SNDS_INT_CSR_INTOFFSET	SNDS_INTOFFSET
#define SNDS_INT_CSR_INTOSET_IRQ			SNDS_INTOSET_IRQ

#define SNDS_INT_CSR_MASK	0x1fffff	

#define SNDS_INT_MODE_IRQ	0x00

/* interrupt levels */
#define INT_LVL_EXTINT0		0	/* External Interrupt0 */
#define INT_LVL_EXTINT1		1	/* External Interrupt1 */
#define INT_LVL_EXTINT2		2	/* External Interrupt2 */
#define INT_LVL_EXTINT3		3	/* External Interrupt3 */
#define INT_LVL_UARTTX0		4	/* UART 0 Transmit Interrupt */
#define INT_LVL_UARTRX0		5	/* UART 0 Receive & Error Interrupt */
#define INT_LVL_UARTTX1		6	/* UART 1 Transmit Interrupt */
#define INT_LVL_UARTRX1		7	/* UART 1 Receive & Error Interrupt */
#define INT_LVL_GDMA0		8	/* GDMA channel 0 interrupt*/
#define INT_LVL_GDMA1		9	/* GDMA channel 1 interrupt */
#define INT_LVL_TIMER0		10	/* Timer 0 Interrupt */
#define INT_LVL_TIMER1		11	/* Timer 1 Interrupt  */
#define INT_LVL_HDLCTxA		12	/* HDLC channel A Tx interrupt*/
#define INT_LVL_HDLCRxA		13	/* HDLC channel A Rx interrupt*/
#define INT_LVL_HDLCTxB		14	/* HDLC channel B Tx interrupt*/
#define INT_LVL_HDLCRxB		15	/* HDLC channel B Rx interrupt*/
#define INT_LVL_BDMATx		16	/* Ethernet controller BDMA Tx Interrupt */
#define INT_LVL_BDMARx		17	/* Ethernet controller BDMA Rx Interrupt */
#define INT_LVL_MACTx		18	/* Ethernet controller MAC Tx Interrupt*/
#define INT_LVL_MACRx		19	/* Ethernet controller MAC Rx Interrupt */
#define INT_LVL_IIC			20	/* IIC -Bus Interrupt */

/* interrupt vectors */

#define INT_VEC_EXTINT0	 IVEC_TO_INUM(INT_LVL_EXTINT0)	/* External Interrupt0 */
#define INT_VEC_EXTINT1	 IVEC_TO_INUM(INT_LVL_EXTINT1)	/* External Interrupt1*/
#define INT_VEC_EXTINT2	 IVEC_TO_INUM(INT_LVL_EXTINT2)	/* External Interrupt2*/
#define INT_VEC_EXTINT3	 IVEC_TO_INUM(INT_LVL_EXTINT3)	/* External Interrupt3*/
#define INT_VEC_UARTTX0	 IVEC_TO_INUM(INT_LVL_UARTTX0)	/* UART 0 Transmit Interrupt */
#define INT_VEC_UARTRX0  IVEC_TO_INUM(INT_LVL_UARTRX0)	/* UART 0 Receive & Error Interrupt */
#define INT_VEC_UARTTX1  IVEC_TO_INUM(INT_LVL_UARTTX1)	/* UART 1 Transmit Interrupt */
#define INT_VEC_UARTRX1  IVEC_TO_INUM(INT_LVL_UARTRX1)	/* UART 1 Receive & Error Interrupt */
#define INT_VEC_GDMA0	 IVEC_TO_INUM(INT_LVL_GDMA0)	/* GDMA channel 0 interrupt*/
#define INT_VEC_GDMA1	 IVEC_TO_INUM(INT_LVL_GDMA1)	/* GDMA channel 0 interrupt*/
#define INT_VEC_TIMER0	 IVEC_TO_INUM(INT_LVL_TIMER0)	/* Timer 0 Interrupt  */
#define INT_VEC_TIMER1	 IVEC_TO_INUM(INT_LVL_TIMER1)	/* Timer 1 Interrupt */
#define INT_VEC_HDLCTxA	 IVEC_TO_INUM(INT_LVL_HDLCTxA)	/* HDLC channel A Tx interrupt */
#define INT_VEC_HDLCRxA  IVEC_TO_INUM(INT_LVL_HDLCRxA)	/* HDLC channel A Rx interrupt*/
#define INT_VEC_HDLCTxB	 IVEC_TO_INUM(INT_LVL_HDLCTxB)	/* HDLC channel B Tx interrupt*/
#define INT_VEC_HDLCRxB	 IVEC_TO_INUM(INT_LVL_HDLCRxB)	/* HDLC channel B Rx interrupt*/
#define INT_VEC_BDMATx	 IVEC_TO_INUM(INT_LVL_BDMATx)	/* Ethernet controller BDMA Tx Interrupt */
#define INT_VEC_BDMARx	 IVEC_TO_INUM(INT_LVL_BDMARx)	/* Ethernet controller BDMA Rx Interrupt */
#define INT_VEC_MACTx	 IVEC_TO_INUM(INT_LVL_MACTx)	/* Ethernet controller MAC Tx Interrupt*/
#define INT_VEC_MACRx	 IVEC_TO_INUM(INT_LVL_MACRx)	/* Ethernet controller MAC Rx Interrupt */
#define INT_VEC_IIC	 	 IVEC_TO_INUM(INT_LVL_IIC)	    /* IIC -Bus Interrupt */


/**********************************************************************************************************
* Cache Definitions
*
*/

#define NON_CACHE_REGION	0x4000000
#define SNDS_CACHE_ENABLE		0x02
#define SNDS_CACHE_4K			0x00
#define SNDS_CACHE_8K			0x10
#define SNDS_CACHE_MODE			0x30
#define SNDS_WRITE_BUFF			0x04
#define SNDS_TAGRAM				0x11000000


/*
 *
 * definitions for the SNDS Timer:
 * two timers clocked from same source and with the same reload overhead
 */
#define SNDS_TIMER_BASE	0x0A800000		/* Address of base of timer */
#define SNDS_TIMER_SYS_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SNDS_TIMER_SYS_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define SNDS_TIMER_AUX_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define SNDS_TIMER_AUX_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)

#define SYS_TIMER_CLK	(SNDS_CPU_SPEED)	/* Frequency of counter/timer */
#define AUX_TIMER_CLK	(SNDS_CPU_SPEED)	/* Frequency of counter/timer */

#define SNDS_RELOAD_TICKS	3		/* three ticks to reload timer */

#define SYS_TIMER_CLEAR(x)	(SNDS_TIMER_T1CLEAR(x))	/* sys Clk is timer 1  */
#define SYS_TIMER_CTRL(x)	(SNDS_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x)	(SNDS_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x)	(SNDS_TIMER_T1VALUE(x))
#define SNDS_TIMER_VALUE_MASK	0xFFFF
#define AUX_TIMER_CLEAR(x)	(SNDS_TIMER_T2CLEAR(x))	/* aux Clk is timer 2  */
#define AUX_TIMER_CTRL(x)	(SNDS_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)	(SNDS_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)	(SNDS_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER1)

/******************************************************************************************
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * Note that it takes 3 ticks to reload the 16-bit counter and we don't
 * accept values that would mean a zero reload value as we don't know what
 * that will do.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value+3))
 * max frequency = rounddown(clock_rate/(min_counter_value+3))
 * i.e. 		     SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4)
 * However, we must set maxima that are sustainable on a running
 * system. Experiments suggest that a 16MHz PID board can sustain a
 * maximum clock rate of 10000 to 10500. The values below have been
 * chosen so that there is a reasonable margin and the BSP passes the
 * test suite.
 */

/*#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0x10001)/0x10002)
 *#if (CPU == ARM710A)
 *#define SYS_CLK_RATE_MAX 15000
 *#else
 *#define SYS_CLK_RATE_MAX 9000
 *#endif
 *#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0x10001)/0x10002)
 *#if (CPU == ARM710A)
 *#define AUX_CLK_RATE_MAX 15000
 *#else
 *#define AUX_CLK_RATE_MAX 9000
 *#endif
 */
#define SYS_CLK_RATE_MIN 10
#define SYS_CLK_RATE_MAX 10000
#define AUX_CLK_RATE_MIN 2
#define AUX_CLK_RATE_MAX 10000
#define SNDS_RESET_RAM_BASE	0x1000000  RAM base in reset memory map */ 

#endif	/* INCsndsh */