entry.s

ZooBoot-4510

#include <c310hw.h>

		.text
		.align

#define FLASH_START 0x40000000

/*----------------------------------
 * DMC Addresses
 * ----------------------------------
 */
#define DRAM_BASE     0x00000000
#define DRAM_SIZE     0x400000
#define DRAM_DATA_START  0x400
#define DRAM_LIMIT    (DRAM_BASE + DRAM_SIZE)

/*----------------------------------
 * OAK RAM Addresses
 * ----------------------------------
 */
#define OAKA_RAM_BASE		0xfd000000
#define OAKA_RAM_SIZE		(48*1024)
#define OAKA_RAM_LIMIT		(OAKA_RAM_BASE+OAKA_RAM_SIZE)

/* ------------------------ List of Exported resources -------------------------*/
		.globl	__entry,_entry
		.globl	__stext,_stext
		.globl _start,start

/*------------------------------------------------------------------------------*/
/*  Define the vector table.*/
/*  The reset vector jumps to the handler code.*/
/*  All others just dead loop on themselves!*/
/*------------------------------------------------------------------------------*/
startoftext:
    B   InitReset   /* reset*/
undefvec:
    B   undefvec    /* Undefined*/
swivec:
    B   swivec      /* SW IRQ*/
pabtvec:
    B   pabtvec     /* Program abort*/
dabtvec:
    B   dabtvec     /* Data abort*/
rsvdvec:
    B   rsvdvec     /* reserved*/
irqvec:
    B   irqvec      /* IRQ*/
fiqvec:
    B   fiqvec      /* FIQ*/

	.long 0x00000007
/*------------------------------------------------------------------------------*/
/*    InitReset. This code is executed with the FLASH at address 0.*/
/*------------------------------------------------------------------------------*/
InitReset:
start:
_start:
_stext:
_entry:
__stext:
__entry:


/*--------------------------------------------------------------------------------------*/
/* Perform A REMAP of the chip. This is only required if we have just performed a BOOT*/
/* DownLoad, but will have no effect under normal conditions.*/
/*--------------------------------------------------------------------------------------*/
	ldr r0, =0xff000000
	mov r1, #1
	str r1, [r0]

	bl config_timer1 /* Initialise Timer 1 channel - this is the DRAM Refresh tick.*/

#ifdef __FLASHED__

/*
	Perform the Remapping of FLASH and DRAM 
*/

/* Copy the Image of the SMC & DMC Memory Controller*/
    adr     r10, InitTableSMC     /* get the address of the SMC chip select image */
    adr     r11, InitTableDMC     /* get the address of the DMC chip select image */
       
/*Load the address where to jump, Zero out the most significant bits.*/
    ldr     r0, =InitRemap        /* get the real jump address ( after remap )*/
	mov	r0, r0, LSL #12
	mov	r0, r0, LSR #12

/*Calculate new PC after the SMC and DMC have been reconfigured.*/
	ldr r1, [r10]
	ldr r2, =0xFFF00000
	and r1, r2, r1

	add r12, r0, r1

    ldmia   r10!, {r0-r4} /*Copy The SMC Image into registers 0,1,2,3*/
    ldmia   r11!, {r5-r8} /*Copy The DMC Image into registers 5,6,7*/
    stmia   r4!, {r0-r3} /*Store the SMC values (r4 contains the base address of the SMC controller)*/
    stmia   r8!, {r5-r7} /*Store the DMC values (r8 contains the base address of the DMC controller)*/

	mov         pc, r12             /* jump and break the pipeline*/

#endif	/* FLASHED */

/*------------------------------------------------------------------------------*/
/*    InitReset.*/
/*------------------------------------------------------------------------------*/
InitRemap:

/* Setup the SVC mode and stack pointer on the top of the internal RAM*/

    mov r0, #(ARM_MODE_SVC | ARM_I_BIT | ARM_F_BIT ) /* No interrupts */
    msr cpsr, r0

   ldr r0, =FLASH_START
   ldr r2, =startoftext
#ifdef __USE_OAK_RAM__
   ldr r13, =OAKA_RAM_LIMIT
   ldr r1, =OAKA_RAM_BASE
#else
   ldr r13, =DRAM_LIMIT
   ldr r1, =DRAM_DATA_START
#endif

    b _main

/*------------------------------------------------------------------------------*/
/* Configure timer 1, This timer channel is connected to DRAM controller*/
/* and is used as the trigger for a DRAM refresh cycle.*/
/* Trashes r1, r2*/
/*------------------------------------------------------------------------------*/
config_timer1:

    ldr r1, =TC0_CMR
    ldr r2, TC_CMR_Value
    str r2, [r1]

    ldr r1, =TC0_RA
    ldr r2, TC_RA_Value
    str r2, [r1]

    ldr r1, =TC0_RC
    ldr r2, TC_RC_Value
    str r2, [r1]

    ldr r1, =TC0_CCR
    ldr r2, TC_CCR_Value
    str r2, [r1]

    ldr r1, =TC_BCR
    ldr r2, TC_CCR_Value
    str r2, [r1]

    mov pc, lr

/*------------------------------------------------------------------------------*/
/* Timer Control Configuration Data*/
/*------------------------------------------------------------------------------*/
TC_CMR_Value:
    .long 0xFFFFC000
TC_RA_Value:
    .long 0x00000047
TC_RC_Value:
    .long 0x00000047
TC_CCR_Value:
    .long 0x00000001


#ifdef __DRAM_32bits__
/*------------------------------------------------------------------------------*/
/* DMC Memory controller configurations -  DRAM 32 bit,  4 chips of 2Mb*/
/*------------------------------------------------------------------------------ */
InitTableDMC:
                .long	0x0000000D      /* DMC MRO */ 
                .long	0x0040000D      /* DMC MR1 */
                .long	0x03            /* DMC CR */
                .long   DMC_BASE        /* DMC Base Address */ 
#else
/*------------------------------------------------------------------------------*/
/* DMC Memory controller configurations - DRAM 16 bits, 2 chips of 2Mb*/
/*------------------------------------------------------------------------------*/
InitTableDMC:
                .long	0x00000005      /* DMC MRO */
                .long	0x00200005      /* DMC MR1 */
                .long	0x02            /* DMC CR */
                .long   DMC_BASE        /* DMC Base Address */ 
        
#endif
        
/*------------------------------------------------------------------------------*/
/* SMC Memory controller configurations -  FLASH 16 bit,  1 chip of 2Mb*/
/*------------------------------------------------------------------------------ */
InitTableSMC:
                .long   0x40002125      /* SMC CSR0 */ 
                .long	0x1000313D      /* SMC CSR1 */
                .long	0x2000313D      /* SMC CSR2 */
                .long	0x3000313D      /* SMC CSR2 */
                .long     SMC_BASE        /* SMC Base Address */