📄 board.inc
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;/**********************************************************************/
;/* */
;/* MODULE: UADSLMCU/KS8947/board.a */
;/* PURPOSE: Board Dependent Macros for Assembly files */
;/* Description: S5N8947 BSP ver.1.0. */
;/* */
;/*--------------------------------------------------------------------*/
;/* COPYRIGHT 2001 SAMSUNG ELECTRONICS. */
;/* INTEGRATED SYSTEMS, INC. */
;/*--------------------------------------------------------------------*/
;/* */
;/* This file contains following sets of definitions: */
;/* */
;/* * The definition of ARM specific register values */
;/* */
;/* * The address definition of the S5N8947 special registers. */
;/* */
;/**********************************************************************/
;************************************************************************
;* Define global variables before assembling. *
;************************************************************************
;/----------------------------------------------------------------------/
;/ Global variable : ENABLE_FIQ_FOREVER /
;/ If the FIQ needs to be enabled for ever, set it to TRUE, otherwise /
;/ set it to FALSE. Common initialzation code will enable the FIQ /
;/ after the disabling all interrupts from the interrupt controller /
;/----------------------------------------------------------------------/
GBLL ENABLE_FIQ_FOREVER
ENABLE_FIQ_FOREVER SETL {FALSE}
;/----------------------------------------------------------------------/
;/ Global variable : ROM_IMAGE /
;/ If you want to make a ROM image, set it to TRUE. /
;/ Otherwise set it to FALSE. /
;/----------------------------------------------------------------------/
GBLL ROM_IMAGE
;When make real ROM code
;ROM_IMAGE SETL {TRUE}
;When make a download program to RAM
ROM_IMAGE SETL {FALSE}
;/----------------------------------------------------------------------/
;/ Global variabal : REMAP /
;/ for remap function /
;/----------------------------------------------------------------------/
GBLL REMAP
;REMAP SETL {TRUE}
REMAP SETL {FALSE}
;/----------------------------------------------------------------------/
;/ Global variable : CACHE_ON /
;/ If you want to enable cache, set it to TRUE /
;/ Otherwise, to disable cache, set it to FALSE. /
;/----------------------------------------------------------------------/
GBLL CACHE_ON
;Don't cache on when make a boot ROM
CACHE_ON SETL {FALSE}
;CACHE_ON SETL {TRUE}
;/----------------------------------------------------------------------/
;/ Global variable : WBUFFER_ON /
;/ If you want to enable write buffer, set it to TRUE /
;/ Otherwise, to disable write buffer, set it to FALSE. /
;/----------------------------------------------------------------------/
GBLL WBUFFER_ON
;Don't write Buffer on when make a boot ROM
;WBUFFER_ON SETL {FALSE}
WBUFFER_ON SETL {TRUE}
;/----------------------------------------------------------------------/
;/ Global variable : WDT_ON /
;/ If you want to enable Watch-dog timer, set it to TRUE /
;/ Otherwise, to disable Watch-dog timer, set it to FALSE. /
;/ by maveric 01/03/03 /
;/----------------------------------------------------------------------/
GBLL WDT_ON
;Don't WDT on when make a boot ROM
;WDT_ON SETL {TRUE}
WDT_ON SETL {FALSE}
;/----------------------------------------------------------------------/
;/ Global variable : USE_pMONT /
;/ If you use pMONT, set it to TRUE, otherwise set it to FALSE. /
;/ This value affect on the interrupt return and call procedures. /
;/----------------------------------------------------------------------/
GBLL USE_pMONT
USE_pMONT SETL {FALSE}
;/----------------------------------------------------------------------/
;/ Global variable : TEST /
;/ For testing the ROM processing /
;/----------------------------------------------------------------------/
GBLL TEST
;TEST SETL {TRUE}
TEST SETL {FALSE}
;************************************************************************
;* Define ARM PSR(Program Status Register) values. *
;************************************************************************
User32Mode EQU &10
FIQ32Mode EQU &11
IRQ32Mode EQU &12
SVC32Mode EQU &13
Abort32Mode EQU &17
Undef32Mode EQU &1b
Mask32Mode EQU &1f
ModeMask EQU &1f
NoInt EQU &c0
FBit EQU &40
IBit EQU &80
TBit EQU &20
;************************************************************************
;* Processor vector definitions. *
;************************************************************************
V_RESET EQU 0
V_UNDEFINED EQU 4
V_SWI EQU 8
V_PREFETCH EQU 12
V_DATAABORT EQU 16
V_RESERVED EQU 20
V_IRQ EQU 24
V_FIQ EQU 28
V_ERROR EQU 32
V_MANBRK EQU 36
V_N_VECTORS EQU 10
;************************************************************************
;* PSR register bit patterns *
;************************************************************************
PSR_Mode_Mask EQU 0x1f
PSR_User_Mode EQU 0x10
PSR_SVC_Mode EQU 0x13
PSR_IRQ_Mode EQU 0x12
PSR_FIQ_Mode EQU 0x11
PSR_Undef_Mode EQU 0x1b
PSR_Abort_Mode EQU 0x17
PSR_I_Bit EQU 0x80
PSR_F_Bit EQU 0x40
PSR_T_Bit EQU 0x20
;************************************************************************
;* KS8947 Special registers definition. *
;************************************************************************
; Base address of special registers.
ASIC_BASE EQU 0x3ff0000
SYSCFG EQU ASIC_BASE
; SYSCFG register values.
STALLBit EQU &1
CacheEnable EQU &2
WBEnable EQU &4
; I/O Port Interface
IOPMOD EQU ASIC_BASE+0x5000
IOPCON0 EQU ASIC_BASE+0x5004 ;Modified by maveric <3.July.2001>
IOPCON1 EQU ASIC_BASE+0x5008 ;Added by maveric <3.July.2001>
IOPDATA EQU ASIC_BASE+0x500C
; UART 0 Registers
UARTLCON0 EQU ASIC_BASE+0xD000
UARTCONT0 EQU ASIC_BASE+0xD004
UARTSTAT0 EQU ASIC_BASE+0xD008
UARTTXH0 EQU ASIC_BASE+0xD00C
UARTRXB0 EQU ASIC_BASE+0xD010
UARTBRD0 EQU ASIC_BASE+0xD014
; Blocked by ydy..11.10 UART1 does not exist in KS8947
; UART 1 Registers
;UARTLCON1 EQU ASIC_BASE+0xE000
;UARTCONT1 EQU ASIC_BASE+0xE004
;UARTSTAT1 EQU ASIC_BASE+0xE008
;UARTTXH1 EQU ASIC_BASE+0xE00C
;UARTRXB1 EQU ASIC_BASE+0xE010
;UARTBRD1 EQU ASIC_BASE+0xE014
; Interrupt Control Registers.
INTMODE EQU ASIC_BASE+0x4000
INTPEND EQU ASIC_BASE+0x4004
INTMASK EQU ASIC_BASE+0x4008
INTPRI0 EQU ASIC_BASE+0x400c
INTPRI1 EQU ASIC_BASE+0x4010
INTPRI2 EQU ASIC_BASE+0x4014
INTPRI3 EQU ASIC_BASE+0x4018
INTPRI4 EQU ASIC_BASE+0x401c
INTPRI5 EQU ASIC_BASE+0x4020
INTOFFSET EQU ASIC_BASE+0x4024
;Add to Watch-dog timer by maveric 01/03/03
;Watch-dog timer control Register
WDCON EQU ASIC_BASE+0x601c
WDCNT EQU ASIC_BASE+0x6020
;WDCON register value
WDT_Enable EQU 0x01
;************************************************************************
;* Added 11.4 from snds100(snds.a) *
;************************************************************************
DRAMBasePtr0 EQU 0x100:SHL:10 ;=0x1000000
DRAMEndPtr0 EQU 0x140:SHL:20 ;=0x1400000
;----------------------------------------------------------------------------------
SRAS2CASDelay0 EQU 1 ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime0 EQU 3 ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr0 EQU 0 ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN0 EQU SNoColumnAddr0:SHL:30
STrc0 EQU SRAS2CASDelay0:SHL:7
STrp0 EQU SRASPrechargeTime0:SHL:8
;
rSDRAMCON0 EQU SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0
;-------------------------------------------------------------
;************************************************************************
;* Align Exception Handler Area for 8 exception sources. *
;* : 0x1000000 ~ 0x1000020 *
;************************************************************************
EXTHND_BASE EQU 0x1000000
^ EXTHND_BASE
HandleReset # 4
HandleUndef # 4
HandleSwi # 4
HandlePrefetch # 4
HandleAbort # 4
HandleReserv # 4
HandleIrq # 4
HandleFiq # 4
END
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