arm7tdmi.h

ZooBoot

#ifndef ARM7TDMI_H
#define ARM7TDMI_H


/* ----- PIO definitions ----- */

typedef struct {
  volatile long per;
  volatile long pdr;
  volatile long psr;
  volatile long reserved_0x0C;
  volatile long oer;
  volatile long odr;
  volatile long osr;
  volatile long reserved_0x1C;
  volatile long reserved_0x20;
  volatile long reserved_0x24;
  volatile long reserved_0x28;
  volatile long reserved_0x2C;
  volatile long sodr;
  volatile long codr;
  volatile long odrs;
  volatile long pdsr;
  volatile long ier;
  volatile long idr;
  volatile long imr;
  volatile long isr;
} pio_t;

#define PIOA_BASE (pio_t*)0xff00c000
#define PIOB_BASE (pio_t*)0xff010000


/* ----- USART definitions ----- */

typedef struct {
  volatile long cr;
  volatile long mr;
  volatile long ier;
  volatile long idr;
  volatile long imr;
  volatile long csr;
  volatile long rhr;
  volatile long thr;
  volatile long brgr;
  volatile long rtor;
  volatile long ttgr;
  volatile long reserverd_0x2C;
  volatile char* rpr;
  volatile long rcr;
  volatile char* tpr;
  volatile long tcr;
  volatile long mc;
  volatile long ms;
} usart_t;

#define USARTA_BASE (usart_t*)0xff018000
#define USARTB_BASE (usart_t*)0xff01c000

/* Control Register bits */
#define RSTRX  (1<<2)
#define RSTTX  (1<<3)
#define RXEN   (1<<4)
#define RXDIS  (1<<5)
#define TXEN   (1<<6)
#define TXDIS  (1<<7)
#define RSTSTA (1<<8)
#define STTBRK (1<<9)
#define STPBRK (1<<10)
#define STTTO  (1<<11)
#define SENDA  (1<<12)

/* Status Register bits */
#define USCLKS_ACLK  (0<<4)
#define USCLKS_ACLK8 (1<<4)
#define USCLKS_EXT   (2<<4)
#define CHRL_FIVE    (0<<6)
#define CHRL_SIX     (1<<6)
#define CHRL_SEVEN   (2<<6)
#define CHRL_EIGHT   (3<<6)
#define SYNC         (1<<8)
#define PAR_EVEN     (0<<9)
#define PAR_ODD      (1<<9)
#define PAR_SPACE    (2<<9)
#define PAR_MARK     (3<<9)
#define PAR_NONE     (4<<9)
#define PAR_MDROP    (6<<9)
#define NBSTOP_1     (0<<12)
#define NBSTOP_1_5   (1<<12)
#define NBSTOP_2     (2<<12)
#define CHMODE_NORM  (0<<14)
#define CHMODE_AECHO (1<<14)
#define CHMODE_LLOOP (2<<14)
#define CHMODE_RLOOP (3<<14)
#define MODE9        (1<<17)
#define CLKO         (1<<18)

/* Channel Status Register bits */
#define RXRDY   (1<<0)
#define TXRDY   (1<<1)
#define RXBRK   (1<<2)
#define ENDRX   (1<<3)
#define ENDTX   (1<<4)
#define OVRE    (1<<5)
#define FRAME   (1<<6)
#define PARE    (1<<7)
#define TIMEOUT (1<<8)
#define TXEMPTY (1<<9)
#define DMSI    (1<<10)


/* ----- Timer definitions ----- */

typedef struct {
  volatile long ccr;
  volatile long cmr;
  volatile long reservered_0x08;
  volatile long reservered_0x0C;
  volatile long cvr;
  volatile long ra;
  volatile long rb;
  volatile long rc;
  volatile long sr;
  volatile long ier;
  volatile long idr;
  volatile long imr;
} timer_t;

#define TIMER0_BASE (timer_t*)0xff014000
#define TIMER1_BASE (timer_t*)0xff014040
#define TIMER2_BASE (timer_t*)0xff014080

/* TC Channel Control Register bits */
#define CLKEN  (1<<0)
#define CLKDIS (1<<1)
#define SWTRG  (1<<2)

/* TC Channel Mode Register bits (Capture Mode, only) */
#define TCCLKS_ACLK2    (0<<0)
#define TCCLKS_ACLK8    (1<<0)
#define TCCLKS_ACLK32   (2<<0)
#define TCCLKS_ACLK128  (3<<0)
#define TCCLKS_ACLK1024 (4<<0)
#define TCCLKS_XC0      (5<<0)
#define TCCLKS_XC1      (6<<0)
#define TCCLKS_XC2      (7<<0)
#define CLKI            (1<<3)
#define BURST_NONE      (0<<4)
#define BURST_XC0       (1<<4)
#define BURST_XC1       (2<<4)
#define BURST_XC2       (3<<4)
#define CPCSTOP         (1<<6)
#define CPCDIS          (1<<7)
#define EEVTEDG_NONE    (0<<8)
#define EEVTEDG_RISING  (1<<8)
#define EEVTEDG_FALLING (2<<8)
#define EEVTEDG_EACH    (3<<8)
#define EEVT_TIOB       (0<<10)
#define EEVT_XC0        (1<<10)
#define EEVT_XC1        (2<<10)
#define EEVT_XC2        (3<<10)
#define ENETRG          (1<<12)
#define CPCTRG          (1<<14)
#define WAVE            (1<<15)
#define ACPA_NONE       (0<<16)
#define ACPA_SET        (1<<16)
#define ACPA_CLEAR      (2<<16)
#define ACPA_TOGGLE     (3<<16)
#define ACPC_NONE       (0<<18)
#define ACPC_SET        (1<<18)
#define ACPC_CLEAR      (2<<18)
#define ACPC_TOGGLE     (3<<18)
#define AEEVT_NONE      (0<<20)
#define AEEVT_SET       (1<<20)
#define AEEVT_CLEAR     (2<<20)
#define AEEVT_TOGGLE    (3<<20)
#define ASWTRG_NONE     (0<<22)
#define ASWTRG_SET      (1<<22)
#define ASWTRG_CLEAR    (2<<22)
#define ASWTRG_TOGGLE   (3<<22)
#define BCPB_NONE       (0<<24)
#define BCPB_SET        (1<<24)
#define BCPB_CLEAR      (2<<24)
#define BCPB_TOGGLE     (3<<24)
#define BCPC_NONE       (0<<26)
#define BCPC_SET        (1<<26)
#define BCPC_CLEAR      (2<<26)
#define BCPC_TOGGLE     (3<<26)
#define BEEVT_NONE      (0<<28)
#define BEEVT_SET       (1<<28)
#define BEEVT_CLEAR     (2<<28)
#define BEEVT_TOGGLE    (3<<28)
#define BSWTRG_NONE     (0<<30)
#define BSWTRG_SET      (1<<30)
#define BSWTRG_CLEAR    (2<<30)
#define BSWTRG_TOGGLE   (3<<30)


typedef struct {
  volatile long bcr;
  volatile long bmr;
} tmrblk_t;

#define TMRBLK_BASE (tmrblk_t*)0xff0140c0

/* TC Block Control Register bits */
#define TMRBLK_SYNC (1<<0)

/* TC Block Mode Register Bits */
#define TC0XC0S_TCLK0 (0<<0)
#define TC0XC0S_NONE  (1<<0)
#define TC0XC0S_TIOA1 (2<<0)
#define TC0XC0S_TIOA2 (3<<0)
#define TC1XC1S_TCLK0 (0<<2)
#define TC1XC1S_NONE  (1<<2)
#define TC1XC1S_TIOA1 (2<<2)
#define TC1XC1S_TIOA2 (3<<2)
#define TC2XC2S_TCLK0 (0<<4)
#define TC2XC2S_NONE  (1<<4)
#define TC2XC2S_TIOA1 (2<<4)
#define TC2XC2S_TIOA2 (3<<4)


/* ----- Ethernet definitions ----- */

typedef struct {
  volatile long ctl;
  volatile long cfg;
  volatile long sr;
  volatile long tar;
  volatile long tcr;
  volatile long tsr;
  volatile long rbqp;
  volatile long reserved_0x1C;
  volatile long rsr;
  volatile long isr;
  volatile long ier;
  volatile long idr;
  volatile long imr;
  volatile long man;
  volatile long reserved_0x38;
  volatile long reserved_0x3C;
  volatile long fra;
  volatile long scol;
  volatile long mcol;
  volatile long ok;
  volatile long seqe;
  volatile long ale;
  volatile long dte;
  volatile long lcol;
  volatile long ecol;
  volatile long cse;
  volatile long tue;
  volatile long cde;
  volatile long elr;
  volatile long rjb;
  volatile long usf;
  volatile long sqee;
  volatile long drfc;
  volatile long reserved_0x84;
  volatile long reserved_0x88;
  volatile long reserved_0x8C;
  volatile long hsh;
  volatile long hsl;
  volatile long sa1l;
  volatile long sa1h;
  volatile long sa2l;
  volatile long sa2h;
  volatile long sa3l;
  volatile long sa3h;
  volatile long sa4l;
  volatile long sa4h;
} ethernet_t;

#define MACA_BASE (ethernet_t*)0xff034000
#define MACB_BASE (ethernet_t*)0xff038000

/* Network Control Register bits */
#define CTL_LB    (1<<0)
#define CTL_LBL   (1<<1)
#define CTL_RE    (1<<2)
#define CTL_TE    (1<<3)
#define CTL_MPE   (1<<4)
#define CTL_CSR   (1<<5)
#define CTL_ISR   (1<<6)
#define CTL_WES   (1<<7)
#define CTL_BP    (1<<8)

/* Network Configuration Register bits */
#define CFG_SPD   (1<<0)
#define CFG_FD    (1<<1)
#define CFG_BR    (1<<2)
#define CFG_CAF   (1<<4)
#define CFG_NBC   (1<<5)
#define CFG_MTI   (1<<6)
#define CFG_UNI   (1<<7)
#define CFG_BIG   (1<<8)
#define CFG_EAE   (1<<9)
#define CFG_CLK8  (0<<10)
#define CFG_CLK16 (1<<10)
#define CFG_CLK32 (2<<10)
#define CFG_CLK64 (3<<10)
#define CFG_CLK   (3<<10)
#define CFG_RTY   (1<<12)

/* Network Status Register bits */
#define SR_LINK   (1<<0)
#define SR_MDIO   (1<<1)
#define SR_IDLE   (1<<2)

/* Transmit Control Register bits */
#define TCR_NCRC  (1<<9)

/* Transmit Status Register bits */
#define TSR_OVR   (1<<0)
#define TSR_COL   (1<<1)
#define TSR_RLE   (1<<2)
#define TSR_IDLE  (1<<3)
#define TSR_BNQ   (1<<4)
#define TSR_COMP  (1<<5)
#define TSR_UND   (1<<6)

/* Receive Status Register bits */
#define RSR_BNA   (1<<0)
#define RSR_REC   (1<<1)
#define RSR_OVR   (1<<2)

/* Interrupt Status Register bits */
#define ISR_DONE  (1<<0)
#define ISR_RCOM  (1<<1)
#define ISR_RBNA  (1<<2)
#define ISR_TOVR  (1<<3)
#define ISR_TUND  (1<<4)
#define ISR_RTRY  (1<<5)
#define ISR_TBRE  (1<<6)
#define ISR_TCOM  (1<<7)
#define ISR_TIDLE (1<<8)
#define ISR_LINK  (1<<9)
#define ISR_ROVR  (1<<10)
#define ISR_HRESP (1<<11)

/* Interrupt Enable Register bits */
#define IER_DONE  (1<<0)
#define IER_RCOM  (1<<1)
#define IER_RBNA  (1<<2)
#define IER_TOVR  (1<<3)
#define IER_TUND  (1<<4)
#define IER_RTRY  (1<<5)
#define IER_TBRE  (1<<6)
#define IER_TCOM  (1<<7)
#define IER_TIDLE (1<<8)
#define IER_LINK  (1<<9)
#define IER_ROVR  (1<<10)
#define IER_HRESP (1<<11)

/* Interrupt Disable Register bits */
#define IDR_DONE  (1<<0)
#define IDR_RCOM  (1<<1)
#define IDR_RBNA  (1<<2)
#define IDR_TOVR  (1<<3)
#define IDR_TUND  (1<<4)
#define IDR_RTRY  (1<<5)
#define IDR_TBRE  (1<<6)
#define IDR_TCOM  (1<<7)
#define IDR_TIDLE (1<<8)
#define IDR_LINK  (1<<9)
#define IDR_ROVR  (1<<10)
#define IDR_HRESP (1<<11)

/* Interrupt Mask Register bits */
#define IMR_DONE  (1<<0)
#define IMR_RCOM  (1<<1)
#define IMR_RBNA  (1<<2)
#define IMR_TOVR  (1<<3)
#define IMR_TUND  (1<<4)
#define IMR_RTRY  (1<<5)
#define IMR_TBRE  (1<<6)
#define IMR_TCOM  (1<<7)
#define IMR_TIDLE (1<<8)
#define IMR_LINK  (1<<9)
#define IMR_ROVR  (1<<10)
#define IMR_HRESP (1<<11)

/* MII definitions */
#define MII_LXT971_OUI	   0x0004de
#define MII_LXT971_MODEL   0x0e
#define MII_LXT971_REV	   0x00
#define MII_LXT971_ID	   ((MII_LXT971_OUI << 10) | (MII_LXT971_MODEL <<4))
#define MII_LXT971_MASK	   0xfffffff0
#define	MII_CTRL_REG	   0x00
#define MII_STS_REG	   0x01
#define MII_PHY_ID1_REG    0x02
#define MII_PHY_ID2_REG    0x03
#define MII_AN_ADVT_REG    0x04
#define MII_AN_LBP_REG	   0x05
#define MII_AN_EXP_REG	   0x06
#define MII_AN_NPT_REG	   0x07
#define MII_AN_LNP_REG	   0x08
#define MII_CFG_REG	   0x10
#define MII_STS2_REG	   0x11
#define MII_IE_REG	   0x12
#define MII_IS_REG	   0x13
#define MII_LEDCFG_REG	   0x14
#define MII_TXCTL_REG	   0x1e
#define MII_ANLPAR_100T4   0x0200 // support 100BT4
#define MII_ANLPAR_100TXFD 0x0100 // support 100BTX full duplex
#define MII_ANLPAR_100TX   0x0080 // support 100BTX half duplex
#define MII_ANLPAR_10TFD   0x0040 // support 10BT full duplex
#define MII_ANLPAR_10T	   0x0020 // support 10BT half duplex
#define MII_ANAR_100T4	   0x0200 // support 100BT4
#define MII_ANAR_100TXFD   0x0100 // support 100BTX full duplex
#define MII_ANAR_100TX	   0x0080 // support 100BTX half duplex
#define MII_ANAR_10TFD	   0x0040 // support 10BT full duplex
#define MII_ANAR_10T	   0x0020 // support 10BT half duplex


/* ----- Ethernet Buffer definitions ----- */

typedef struct {
  unsigned long addr,size;
} rbf_t;

#define RBF_ADDR      0xfffffffc
#define RBF_OWNER     (1<<0)
#define RBF_WRAP      (1<<1)
#define RBF_BROADCAST (1<<31)
#define RBF_MULTICAST (1<<30)
#define RBF_UNICAST   (1<<29)
#define RBF_EXTERNAL  (1<<28)
#define RBF_UNKOWN    (1<<27)
#define RBF_SIZE      0x07ff
#define RBF_LOCAL4    (1<<26)
#define RBF_LOCAL3    (1<<25)
#define RBF_LOCAL2    (1<<24)
#define RBF_LOCAL1    (1<<23)

#define RBF_FRAMEMAX 10
#define RBF_FRAMEMEM 0xfc000000
#define RBF_FRAMELEN 0x600

#define RBF_FRAMEBTD RBF_FRAMEMEM
#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))


#endif