📄 masks860.h
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*-----------------------------------------------------------*
* NOTE: The real-time clock alarm (RTCAL) is a 32-bit R/W *
* register. When the value of the RTC is equal to the *
* value programmed in the alarm register, a maskable *
* interrupt is generated *
*-----------------------------------------------------------*/
#define RTCAL_ALARM 0xFFFFFFFF
/*--------------------------------------------------------*
* Periodic Interrupt Status and Control Register (PISCR) *
*--------------------------------------------------------*/
#define PISCR_PIRQ 0xFF00 /* Periodic Interrupt Request Level */
#define PISCR_PS 0xFF80 /* Periodic Interrupt Status */
#define RESERVED71 0x0078
#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
/*---------------------------------------------------------------*
* Periodic Interrupt Timer Count (PITC) *
*---------------------------------------------------------------*
* NOTE: Contains the 16 bits to be loaded in a modulus counter. *
* The register is always R/W. *
*---------------------------------------------------------------*/
#define PITC_PITC 0xFFFF0000
#define RESERVED72 0x0000FFFF
/*----------------------------------------------------------------*
* Periodic Interrupt Timer Register (PITR) *
*----------------------------------------------------------------*
* NOTE: A read-only register that shows the current value in the *
* periodic interrupt down counter. Reads or writes to *
* this register have no effect on the register or counter *
*----------------------------------------------------------------*/
#define PITR_PIT 0xFFFF0000
#define RESERVED73 0x0000FFFF
/*-------------------------------------------------------------------------*
* CLOCKS AND RESET *
*-------------------------------------------------------------------------*/
/*--------------------------------------*
* System Clock Control register (SCCR) *
*--------------------------------------*/
#define RESERVED74 0x80000000
#define SCCR_COM 0x60000000 /* Clock Output Mode */
#define RESERVED75 0x1C000000
#define SCCR_TBS 0x02000000 /* Timebase Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
#define SCCR_CRQEN 0x00400000 /* CPM requect enable */
#define SCCR_PRQEN 0x00200000 /* Power management request enable */
#define RESERVED76 0x00180000
#define SCCR_EBDF 0x00060000 /* CLKOUT frequency */
#define RESERVED77 0x00018000
#define SCCR_DFSYNC 0x00006000 /* Division factor of SyncCLK */
#define SCCR_DFBRG 0x00001800 /* Division factor of BRGCLK */
#define SCCR_DFNL 0x00000700 /* Division factor low frequency */
#define SCCR_DFNH 0x000000D0 /* Division factor high frequency */
#define RESERVED78 0x0000001F
/*-----------------------------------------------------*
* PLL, Low Power, and Reset Control Register (PLPRCR) *
*-----------------------------------------------------*/
#define PLPRCR_MF 0xFFF00000 /* Multiplication factor bits */
#define RESERVED79 0x000F0000
#define PLPRCR_SPLSS 0x00008000 /* SPLL lock status sticky bits */
#define PLPRCR_TEXPS 0x00004000 /* TEXP status bit */
#define RESERVED80 0x00002000
#define PLPRCR_TMIST 0x00001000 /* Timers interrupt status */
#define RESERVED81 0x00000800
#define PLPRCR_CSRC 0x00000400 /* Clock source bit */
#define PLPRCR_LPM 0x00000300 /* Low power mode select bits */
#define PLPRCR_CSR 0x00000080 /* Checkstop reset enable */
#define PLPRCR_LOLRE 0x00000040 /* Loss of lock reset enable */
#define PLPRCR_FIOPD 0x00000020 /* Force I/O pull-down */
#define RESERVED82 0x0000001F
/*-----------------------------*
* Reset status register (RSR) *
*-----------------------------*/
#define RSR_EHRS 0x80 /* External hard reset status */
#define RSR_ESRS 0x40 /* External soft reset status */
#define RSR_LLRS 0x20 /* Loss of lock status */
#define RSR_SWRS 0x10 /* Software watchdog reset status */
#define RSR_CSRS 0x08 /* Check stop reset status */
#define RSR_DBHRS 0x04 /* Debug port hard reset status */
#define RSR_DBSRS 0x02 /* Debug port soft reset status */
#define RSR_JTRS 0x01 /* JTAG reset status */
/*-------------------------------------------------------------------------*
* SYSTEM INTEGRATION TIMERS KEYS *
*-------------------------------------------------------------------------*
* NOTE: Bit masks are not provided for System Integration Timers Keys or *
* Clocks and Reset Keys. A write of 0x55CCAA33 to a key's memory *
* address will change it to the open state. A write of any other *
* data to a key's location will change it to the locked state. At *
* power-on reset, all keys (except for real-time clock related *
* registers) are in the open state. *
*-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------*
* I2C *
*-------------------------------------------------------------------------*/
/*---------------------------*
* I2C Mode Register (I2MOD) *
*---------------------------*/
#define RESERVED83 0xC0
#define I2MOD_REVD 0x20 /* Reverse Data */
#define I2MOD_GCD 0x10 /* General Call Disable */
#define I2MOD_FLT 0x08 /* Clock filter */
#define I2MOD_PDIV 0x06 /* Pre Divider */
#define I2MOD_EN 0x01 /* Enable I2C */
/*------------------------------*
* I2C Address Register (I2ADD) *
*------------------------------*/
#define I2ADD_SAD 0xFE /* Slave Address */
#define RESERVED84 0x01
/*--------------------------*
* I2C BRG Register (I2BRG) *
*--------------------------*/
#define I2BRG_DIV 0xFF /* Division Ratio */
/*------------------------------*
* I2C Command Register (I2COM) *
*------------------------------*/
#define I2COM_STR 0x80 /* Start Transmit */
#define RESERVED85 0x7E
#define I2COM_M/S 0x01 /* Master Slave */
/*----------------------------*
* I2C Event Register (I2CER) *
*----------------------------*/
#define RESERVED86 0xE0
#define I2CER_TXE 0x10 /* Tx Error */
#define RESERVED87 0x80
#define I2CER_BSY 0x04 /* Busy Condition */
#define I2CER_TXB 0x02 /* Tx Buffer */
#define I2CER_RXB 0x01 /* Rx Buffer */
/*------------------------------------------------------------------*
* I2C Mask Register (I2CMR) *
*------------------------------------------------------------------*
* NOTE: The I2C mask register is an 8-bit read/write register that *
* has the same bit formats as the I2CER. If a bit in the *
* I2CMR is 1, the corresponding interupt in the I2CER is *
* enabled. If the bit is zero, the corresponding interrupt *
* in the I2CER is marked. This register is cleared at reset. *
* *
*------------------------------------------------------------------*/
#define RESERVED88 0xE0
#define I2CMR_TXE 0x10 /* Tx Error */
#define RESERVED89 0x80
#define I2CMR_BSY 0x04 /* Busy Condition */
#define I2CMR_TXB 0x02 /* Tx Buffer */
#define I2CMR_RXB 0x01 /* Rx Buffer */
/*-------------------------------------------------------------------------*
* DMA *
*-------------------------------------------------------------------------*/
/*--------------------------------------------------------------------*
* SDMA Address Register (SDAR) *
*--------------------------------------------------------------------*
* NOTE: Bit masks are not provived for SDMA Address Register (SDAR). *
* The 32-bit read-only SDMA Address Register shows the system *
* address that is accessed during an SDMA bus error. It is *
* undefined at reset. *
*--------------------------------------------------------------------*/
/*-----------------------------*
* SDMA Status Register (SDSR) *
*-----------------------------*/
#define SDSR_SBER 0x80 /* SDMA Channel Bus Error */
#define SDSR_RINT 0x40 /* Reserved Interrupt */
#define RESERVED90 0x3C
#define SDSR_DSP2 0x02 /* DSP Chain 2 Interrupt */
#define SDSR_DSP1 0x01 /* DSP Chain 1 Interrupt */
/*---------------------------------------------------------------------*
* SDMA Mask Register (SDMR) *
*---------------------------------------------------------------------*
* NOTE: Bit masks are not provided for the SDMA Mask Register (SDMR). *
* The SDMA Mask Register is an 8-bit read/write register with *
* the same bit format as the SDMA status register. If a bit in *
* the SDMA mask register is a 1, the corresponding interrupt in *
* the event register is enabled. If the bit is zero, the *
* corresponding interrupt in the event register is masked. This *
* register is cleared at reset. *
*---------------------------------------------------------------------*/
/*-------------------------------*
* IDMA1 Status Register (IDSR1) *
*-------------------------------*/
#define RESERVED91 0xF8
#define IDSR1_OB 0x04 /* Out of buffers */
#define IDSR1_DONE 0x02 /* IDMA transfer done */
#define IDSR1_AD 0x01 /* Auxiliary done */
/*---------------------------------------------------------------------*
* IDMA1 Mask Register (IDMR1) *
*---------------------------------------------------------------------*
* NOTE: Bit masks are not provided for the IDMA1 Mask Register. The *
* IDMA mask register is an 8-bit read/write register with *
* the same bit format as the IDSR. If a bit in the IDMR is a 1, *
* the corresponding interrupt in the status register is *
* enabled. If the bit is zero, the corresponding interrupt in *
* the status register is masked. This register is cleared at *
* reset. *
*---------------------------------------------------------------------*/
/*-------------------------------*
* IDMA2 Status Register (IDSR2) *
*-------------------------------*/
#define RESERVED92 0xF8
#define IDSR2_OB 0x04 /* Out of buffers */
#define IDSR2_DONE 0x02 /* IDMA transfer done */
#define IDSR3_AD 0x01 /* Auxiliary done */
/*----------------------------------------------------------------------*
* IDMA2 Mask Register (IDMR2) *
*----------------------------------------------------------------------*
* NOTE: Bit masks are not provided for the IDMA2 Mask Register. The *
* IDMA mask register is an 8-bit read/write register with *
* the same bit format as the IDSR. If a bit in *
* the IDMR is a 1, the corresponding interrupt in *
* the status register is enabled. If the bit is zero, the *
* corresponding interrupt in the status register is masked. *
* This register is cleared at reset. *
*----------------------------------------------------------------------*/
/*-------------------------------------------------------------------------*
* CPM INTERRUPT CONTROL *
*-------------------------------------------------------------------------*/
/*-------------------------------------*
* CP Interrupt Vector Register (CIVR) *
*-------------------------------------*/
#define CIVR_VN 0xF800 /* Vector number */
#define RESERVED93 0x07FE
#define CIVR_IACK 0x0001 /* Interrupt acknowledge */
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