init_ser.inc

声音均衡器的源代码程序

**************************************************************************
* FILENAME: INIT_SER.INC
* This include file includes the SPC1 register configuration.
**************************************************************************
* Bit    Name    Function
* 0      Reserved Always read as 0
* 1      DLB     Digital loop back : 0 -> Disabled, 1 _. Enabled
* 2      FO      Format bit: 0 - > data transfered as 8 bit bytes, 1 -> 16 bit words
* 3      FSM     Frame sync pulse: 0 -> serial port in continuous mode, 1 -> FSM is required 
* 4      MCM     Clock mode bit: 0 -> CLKX obtained from CLKX pin 1-> CLKX obtained from CLKX
* 5      TXM     Transmit mode bit: 0 -> Frame sync pulses generated externally and supplied on FSX pin,   1-> Internally generated frame sync pulses out on FSX pin
* 6      XRST    Transmit reset bit: 0 -> reset the serial port, 1-> bring serial port out of reset
* 7      RRST    Receive reset bit:  0 -> reset the serial port, 1-> bring serial port out of reset
* 8      IN0     Read-only bit reflecting the state of the CLKR pin
* 9      IN1     Read-only bit reflecting the state of the CLKX pin
* 10     RRDY    Transition from 0 to 1 indicates data is ready to be read
* 11     XRDY    Transition from 0 to 1 indicates data is ready to be sent
* 12     XSREMPTY Transmit shift register empty  ( Read-only) 0 -> tramsitter has experienced underflow, 1-> has not expereinced underflow
* 13     RSRFUL  Receive shift register full flag   (Read-only):    0 -> Receiver has experienced overrun,   1-> receiver has not experienced overrun
* 14     SOFT    Soft bit - 0 -> immdeiate stop, 1-> stop after word completion
* 15     FREE    Free run bit: 0 -> behaviour depends on SOFT bit, 1-> free run regardless of SOFT bit
* The system has the following configuration:
*       Uses 16-bit data => FO = 0
*       Operates in burst mode => FSM = 1
*       CLKX is derived from CLKX pin => MCM = 0
*       Frame sync pulses are generated externally by the AIC => TXM = 0
* Therefore, to reset the serial port, the SPC field would have
*       0000 0000 0000 1000
* To pull the serial port out of reset, the SPC field would have
*       0000 0000 1100 1000

K_0              .set    00000000b << 8           ; bits 15-8 to 0 at reset
K_RRST           .set    0b << 7                  ; First write to SPC1 is 0 second write is 1
K_XRST           .set    0b << 6                  ; First write to SPC1 is 0 second write is 1
K_TXM            .set    0b << 5
K_MCM            .set    0b << 4
K_FSM            .set    1b << 3                  ; Frame Sync mode
K_ZERO           .set    000b << 0
K_SERIAL_RST     .set    K_0|K_RRST|K_XRST|K_TXM|K_MCM|K_FSM|K_ZERO      ; first write to SPC1 regsiter


K_RRST1          .set    1b << 7                  ; second write to SPC1
K_XRST1          .set    1b << 6                  ; second write to SPC1

K_SERIAL_OUT_RST .set    K_0|K_RRST1|K_XRST1|K_TXM|K_MCM|K_FSM|K_ZERO    ; second write to SPC1 regsiter