dsp28_revisionhistory.txt

TI公司的2812dsp所有程序

Alpha TMX Header Files

Revision History:

Rev .58 Alpha - July 22, 2002

    -  DSP28_Device.h
       Added #define for CPU Speed and macro to calcualate a delay in micro-seconds

    -  DSP28_Adc.c
       Added InitAdc Function

    -  DSP28_Ev.h
       Fixed register missing register bits in GPTCONA 

    -  DSP28_PieCtrl.h
       DSP28_GlobalPrototypes.h
       DSP28_PieCtrl.c
       DSP28_PieVect.c
       example files
       Changed "PieCtrl" to "PieCtrlRegs" for consistancy with other structure names. 

     - DSP28_CpuTimers.h
       Commented out code for CPU Timer1 and CPU Timer2. These two timers 
       are are reserved for use with DSP BIOS and other realtime operating
       systems. Using these two timers in your application will cause
       cause problems integrating DSP-BIOS or another realtime OS. 

     - Example_28xDevice.c
       Changed this example to use CPU Timer 0 instead of CPU Timer 2. 

     - DSP28_Adc.h
       Updated register names to match the current datasheet.

     - EzDSP_RAM_lnk.cmd, F2812.cmd, F2810:

       * Added RESET memory section that can be used when booting from XINTF Zone7
       * .reset and vectors type = DSECT These sections will not normally be used
         when booting from the internal boot ROM.  
       * Changed IQ math table in ROM section to type = NOLOAD 
       * Added codestart section and BEGIN memory region for redirecting code execution
         when booting to Flash. The code for this section can be found in: DSP28_CodeStartBranch.asm 
       * Fixed FLASHA length.  
       * Removed CPU Timer1 and CPU Timer2 section allocation (reserved for BIOS apps) 
 
     - New Files:
       DSP28_CodeStartBranch.asm.  Branch for redirecting "boot to flash" code
       DSP28_DBGIER.asm            Assembly routine for manipulating DBGIER register from C
       DSP28_usDelay.asm           Assembly routine for implementing a delay in micro-seconds


Rev .57 Alpha - May 20, 2002

     - DSP28_SysCtrl.c
       Added initialization of RAM control registers.  On TMX samples to
       get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 
       internal control registers bits have to be enabled. The bits are 
       in Device emulation registers.  

     - DSP28_Ev.h
       Fixed several cut/paste errors for GPIO G registers.  The bit names were 
       mistakenly marked as GPIOF instead of GPIOG.  Registers fixed:
       GPGDIR_BITS, GPGDAT_BITS, GPGSET_BITS, GPGCLEAR_BITS, GPGTOGGLE_BITS

     - DSP28_Device.h
       Added generic bit field definitions.  

       #define	BIT0		0x0001
       #define	BIT1		0x0002
       .... 
       #define	BIT15		0x8000

       This will be useful in creating mask values to set/clear bits within registers.
       For example:  

                   PieCtrl.PIEACK.all = (BIT1 | BIT2 | BIT15);

       Is the same as:

                   PieCtrl.PIEACK.all = 0x8003;
                    

Rev .56 Alpha - May 20, 2002

     Fixes from Alpha .55

     - Added this file to log future corrections.
      
     - linker command files:
       Peripheral frame 1 and 2 had their names reversed in the comments

     - DSP28_GlobalVariableDefs.c
       Corrected case typo: "PIEVectTable" should be "PieVectTable".

     - DSP28_Ev.h
       EVA & EVB structure definitions, there was an extra reserved word allocated, 
       so the subsequent registers were off by one address.  
       The issue is in both v0.54 and v0.55.


Rev .55 Alpha - Initial Alpha release for eZdsp sampling