receive.vhd

一个hdlc发送模块的编码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY receive IS

	PORT
	(
		Clk						: IN	STD_LOGIC;
		SerIn					: IN 	STD_LOGIC;
		--Enable					: IN	STD_LOGIC;
		--WrFlash					: IN	STD_LOGIC;
		Reset					: IN	STD_LOGIC;
		WrReq					: OUT	STD_LOGIC;
		ParData					: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0)		
	);
	
END receive;

ARCHITECTURE behav OF receive IS

type state is(idle0, idle1, idle2, idle3, idle4, idle5, idle6, idle7);
--type crc_state is(idle0, idle1, idle2, idle3, idle4, idle5);

signal para_buf	:	std_logic_vector(47 downto 0);
signal tran_start, crc_start, rec_start	:	std_logic	:=	'0';

signal cur_flag_sta		:	state := idle0;
signal cur_data_sta		:	state := idle0;

signal wr_sta			:	state ;= idle0;

	
BEGIN
--------------JUSTIFY THE BEGINING OF RECEIVING------------
	PROCESS (clk,crc_start,reset)
	BEGIN
		if(reset = '1')
			then crc_start <= '0';
				 cur_flag_sta <= idle0;
				 rec_start <= '0';
		elsif(crc_start = '1')
			then cur_flag_sta <= idle7;
		elsif(clk'event and clk = '1') then
			case cur_flag_sta is
				when idle0 => if(serin = '0') then cur_flag_sta <= idle1;
								else cur_flag_sta <= idle0;
							  end if;
				when idle1 => if(serin = '1') then cur_flag_sta <= idle2;
								else cur_flag_sta <= idle0;
						  	  end if;
				when idle2 => if(serin = '1') then cur_flag_sta <= idle3;
								else cur_flag_sta <= idle0;
							  end if;
				when idle3 => if(serin = '1') then cur_flag_sta <= idle4;
								else cur_flag_sta <= idle0;
						   	  end if;
				when idle4 => if(serin = '1') then cur_flag_sta <= idle5;
								else cur_flag_sta <= idle0;
							  end if;
				when idle5 => if(serin = '1') then cur_flag_sta <= idle6;
								else cur_flag_sta <= idle0;
						 	  end if;
				when idle6 => if(serin = '1') then cur_flag_sta <= idle7;
								else cur_flag_sta <= idle0;
							  end if;
				when idle7 => if(serin = '0') then crc_start <= '1';
												   rec_start <= '1';
								   				   cur_flag_sta <= idle7;
								else cur_flag_sta <= idle0;
							  end if;
			end case;
		end if;
	END PROCESS;
-----------------PROCESS END--------------------

-----------------BEGIN RECEIVING----------------
process(clk, rec_start)
begin
	if(clk'event and clk = '1') then
		case cur_data_sta is
			when idle0 => if(serin = '0') then cur_flag_sta <= idle1;
							else cur_flag_sta <= idle0;
						  end if;
			when idle1 => if(serin = '1') then cur_flag_sta <= idle2;
							else cur_flag_sta <= idle0;
						  end if;
			when idle2 => if(serin = '1') then cur_flag_sta <= idle3;
							else cur_flag_sta <= idle0;
						  end if;
			when idle3 => if(serin = '1') then cur_flag_sta <= idle4;
							else cur_flag_sta <= idle0;
					   	  end if;
			when idle4 => if(serin = '1') then cur_flag_sta <= idle5;
							else cur_flag_sta <= idle0;
						  end if;
			when idle5 => if(serin = '1') then cur_flag_sta <= idle6;
							else cur_flag_sta <= idle0;
					 	  end if;
			when idle6 => if(serin = '1') then cur_flag_sta <= idle7;
							else cur_flag_sta <= idle0;
						  end if;

		


-----------------BEGIN CRC-16 CHECK--------------
process(clk,crc_start,reset)
signal reg16 : std_logic_vector(15 downto 0);
begin
	if(reset = '1') then 
		reg16 <= x"0000";
	elsif(clk'event and clk = '1') then 
		if(crc_start = '1') then 
			case cur_crc_sta is
				when idle0 => if serin = '1' then cur_crc_sta <= idle1; 
		
	end if;
end process;
---------------PROCESS END----------------------

---------------DELIVER THE DATA TO FIFO---------------
process(clk, tran_start,reset)
begin
	if(reset = '1') then
		wr_sta <= idle0;
	elsif(clk'event and clk = '1') then
		if(tran_start = '1') then
			case wr_sta is
				when idle0 => wrreq <= '1'; 
							  paradata <= para_buf(47 downto 32);
							  wr_sta <= idle1;
				when idle1 => wrreq <= '1';
							  wr_sta <= idle2;
				when idle2 => wrreq <= '1';
							  paradata <= para_buf(31 downto 16);
							  wr_sta <= idle3;
				when idle3 => wrreq <= '1';
							  wr_sta <= idle4;
				when idle4 => wrreq <= '1';
							  paradata <= para_buf(15 downto 0);
							  wr_sta <= idle5;
				when idle5 => wrreq <= '0';
							  wr_sta <= idle5;
			end case;
		end if;
	end if;
end process;
---------------PROCESS END-----------------------
	
END behav;