send.vhd

一个hdlc的接受模块代码

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY send IS

	PORT
	(
		ParData					: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		Clk						: IN	STD_LOGIC;
		Rdstart					: IN	STD_LOGIC;
		Rdend					: IN	STD_LOGIC;
		Rdreq					: out	STD_LOGIC;
		SerQ					: OUT 	STD_LOGIC
	);
	
END send;

ARCHITECTURE behav OF send IS
	constant crc_init	:	std_logic_vector(15 downto 0) := "000000000000000";
	constant gener	: std_logic_vector(15 downto 0) := "1000000001000011"
	SIGNAL	Q_buf	: STD_LOGIC;
	signal  flag_st1, flag_end1, flag_st2, flag_end2	: std_logic := '0';
	signal  out_reg	: std_logic_vector(7 downto 0)	:= "01111110";

BEGIN
	SerQ <= Q_buf;

------send model start---------
	PROCESS (Rdstart)
	BEGIN
		if(Rdstart'event and Rdstart = '1')
			then flag_st1 <= '1';	
		end if;
	END PROCESS;
--------send model end-----------

-------flag process start-----
process(flag_st1, flag_end1, flag_st2, flag_end2, clk)      
	variable count : integer range 0 to 8 := 0;
	begin
		if(clk'event and clk = '1')
			then if(flag_st1 = '1' and flag_end1 = '0')
					then if(count < 8)
						   then q_buf <= out_reg(7);
						     	out_reg(7 downto 0) <= out_reg(6 downto 0) & out_reg(7);
						     	count  := count + 1;
						 else count := 0;
							  flag_end1 <= '1';
						 end if;
				 elsif(flag_st2 = '1' and flag_end2 = '0')
					then if(count < 8)
						   then q_buf <= out_reg(7);
						     	out_reg(7 downto 0) <= out_reg(6 downto 0) & out_reg(7);
						     	count := count + 1;
						 else count := 0;
							  flag_end2 <= '1';
						 end if;

				 end if;
		end if;	
	end process;
-------flag process end---------

--------data process start-------
process(flag_end1, flag_st2, clk)
variable 	cont	:	integer range	0 to 49	:= 	0;
signal 	 	out_reg	: 	std_logic_vector(16 downto 0) := "00000000000000000";
signal 		pre_data:	std_logic_vector(15 downto 0);
begin
	if(flag_end1'event and flag_end1 = 1)
		then cont := 0;
			 rdreq <= '1';
	elsif(clk'event and clk = '1')
		then if(flag_end1 = '1' and flag_st2 = '0')
				then if(cont = 0 or cont = 16 or cont = 32)
						then cont := cont + 1;
							 pre_data <= pardata;
						end if;
					 if(cont < 47)
						then if(out_reg(15) = 1)
								then ser_q <= pardata(15);
									 out_reg(15 downto 0) <= out_reg(15 downto 0) xor gener;
							 end if;
							 out_reg(15 downto 0) <= out_reg(14 downto 0) & pre_data(15);
							 pre_data(15 downto 0) <= pre_data(14 downto 0) & '0';
					 elsif(cont < 63)
						then if(out_reg(15) = 1)
								then ser_q <= pardata(15);
									 out_reg(15 downto 0) <= out_reg(15 downto 0) xor gener;
							 end if;
							 out_reg(15 downto 0) <= out_reg(14 downto 0) & pre_data(15);
							 pre_data(15 downto 0) <= pre_data(14 downto 0) & '0';

						then cont := 0;
						     rdreq <= '0';
						     flag_st2 <= '1';
					 end if;
			 end if;
	end if;
end process;			 		 

		
END behav;