rfc1936.txt

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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996


Summary

   This note describes the design of a hardware Internet Checksum that
   can be implemented in an inexpensive PLD, achieving 1.26 Gbps. This
   design has been implemented in the PC-ATOMIC host interface hardware
   [8]. We believe this design is of general use to the Internet
   community.

Security Considerations

   Security considerations are not addressed here. The Internet Checksum
   is not intended as a security measure.

Acknowledgements

   The authors would like to thank the members of the "High-Performance
   Computing and Communications", notably Mike Carlton, and "Advanced
   Systems" Divisions at ISI for their assistance in the development of
   the hardware, and this memo.

References

   [1] Braden, R., Borman, D., and Partridge, C., "Computing the
       Internet Checksum," Network Working Group RFC-1071, ISI, Cray
       Research, and BBN Labs, Sept. 1988.

   [2] Mallory, T., and Kullberg, A., "Incremental Updating of the
       Internet Checksum," Network Working Group RFC-1141, BBN Comm.,
       Jan. 1990.

   [3] Plummer, W., "TCP Checksum Function Design," IEN-45, BBN, 1978,
       included as an appendix in RFC-1071.

   [4] Postel, Jon, "Internet Protocol," Network Working Group RFC-
       791/STD-5, ISI, Sept. 1981.

   [5] Postel, Jon, "User Datagram Protocol," Network Working Group
       RFC-768/STD-6, ISI, Aug. 1980.

   [6] Postel, Jon, "Transmission Control Protocol," Network Working
       Group RFC-793/STD-7, ISI, Sept. 1981.

   [7] Rijsinghani, A., "Computation of the Internet Checksum via
       Incremental Update," Network Working Group RFC-1624, Digital
       Equipment Corp., May 1994.

   [8] Touch, J., "PC-ATOMIC", ISI Tech. Report. SR-95-407, June 1995.




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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996


Authors' Addresses

   Joe Touch
   University of Southern California/Information Sciences Institute
   4676 Admiralty Way
   Marina del Rey, CA 90292-6695
   USA
   Phone: [phone] x151
   Fax:   [phone]
   URL:   http://www.isi.edu/~touch
   EMail: [e-mail]


   Bruce Parham
   University of Southern California/Information Sciences Institute
   4676 Admiralty Way
   Marina del Rey, CA 90292-6695
   USA
   Phone: [phone] x101
   Fax:   [phone]
   EMail: [e-mail]






























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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996


Appendix A: PLD source code

The following is the PLD source code for an AMD MACH-435 PLD. The
MACH-435 is composed of 8 22V10-equivalent PLD blocks, connected by a
configurable internal matrix.


---- (PLD source code follows) ----

TITLE    PC-ATOMIC IP Sum Accelerator - 1-clock 2- and 3-bit 26 ns version
PATTERN  ip_sum
REVISION 1.01
AUTHOR   J. Touch & B. Parham
COMPANY  USC/ISI
DATE     06/21/94

CHIP    ip_sum          MACH435

; accumulates in 1 clock (1 level of logic)
;
; resources allocated to reduce fitting time
;
; uses an input register "dl" to latch the data bus values on rising edge
; accumulates a hi/lo ones-complement sum in register "q"
; the input and output are accessed via bidirectional pins "dq"
;
; uses 2 groups of 6 carry bit registers "cy"
;
; use 3-bit full-adders with carry lookahead (settles in 6 clocks)
; group 16 bits as      [000102 030405 0607 080910 111213 1415]
;                       [161718 192021 2223 242526 272829 3031]
;
; locking the pins down speeds up fitting and is designed to force
; 4-bit components into single "segments" of the PLD.
; we could have indicated the same thing via:
;       GROUP MACH_SEG_A        dq[6..0]
;       GROUP MACH_SEG_B        dq[14..8]
;       GROUP MACH_SEG_C        dq[22..16]
;       GROUP MACH_SEG_D        dq[30..24]

;
; control pins:
;
PIN     20      clk             ; adder clock
PIN     62      ip_add          ; add current data to sum
PIN     83      ip_sum_ena      ; output current sum
PIN     41      ip_clr          ; clear current sum
PIN 23  ip_dclk                 ; input data latch (tied to clk, or not)



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;
; dq are data bus pins
; dl is the input register
;
PIN     [9..3]          dq[6..0] IPAIR dl[6..0]         ; IO port
PIN     [18..12]        dq[14..8] IPAIR dl[14..8]       ; IO port
PIN     [30..24]        dq[22..16] IPAIR dl[22..16]     ; IO port
PIN     [39..33]        dq[30..24] IPAIR dl[30..24]     ; IO port
PIN     ?       dq[31,23,15,7] IPAIR dl[31,23,15,7]     ; IO port

;
; q  is the partial checksum register
; dl is the input register
; dq are the data bus pins
;
NODE    ?       q[31..0] OPAIR dq[31..0]        ; internal data in reg
NODE    ?       dl[31..0] REG                   ; input reg

;
; cy are the carry register bits
;
NODE    ?       cy[31,29,26,23,21,18,15,13,10,7,5,2] REG
                                                ;1-bit internal carry bits

EQUATIONS

;
; .trst is the tri-state control, 0 means these are always inputs
;
ip_add.trst             = 0
ip_clr.trst             = 0
ip_sum_ena.trst         = 0

;
; grab data to the input register on every clock (irrelevant if invalid)
;
dl[31..0].clkf          = ip_dclk       ; grab data all the time
        ; don't use setf, rstf, or trst for dl
        ; we want dl to map to input registers, not internal cells
        ; besides, input registers don't need setf, rstf, or trst

;
; control of the checksum register
;
dq[31..0].clkf          = clk                   ; clk clocks everything
dq[31..0].setf          = gnd                   ; never preset registers
dq[31..0].rstf          = ip_clr                ; clear on reset
dq[31..0].trst          = ip_sum_ena            ; ena outputs sum - read



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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996


;
; control for the carry register
;
cy[31,29,26,23,21,18,15,13,10,7,5,2].clkf       = clk
cy[31,29,26,23,21,18,15,13,10,7,5,2].setf       = gnd    ; never preset
cy[31,29,26,23,21,18,15,13,10,7,5,2].rstf       = ip_clr ; clear on reset

;
; INPUT DATA LATCH
; nothing fancy here - grab all inputs when ip_add signal is high
; i.e., grab data in input register
;
dl[31..0]             := dq[31..0]

;
; COMBINATORIAL ADDER
;
; built as a series of 2-bit and 3-bit (carry-lookahead) full-adders
; with carries sent to the carry register "pipeline"
;
; sum[n] are sum bits
; cy[m] are carry bits
; ":+:" is XOR

;
; SUM[0] = (A0 :+: B0 :+: CARRY_IN)
;
; CY[0] = ((A0 * B0) + ((A0 :+: B0) * CARRY_IN))
;
; actually, the latter can be rewritten as
;
; CY[0] = ((A0 * B0) + ((A0 + B0) * CARRY_IN))
;
; because the XOR won't be invalidated by the AND case, since the
; result is always 1 from the first term then anyway
; this helps reduce the number of XOR terms required, which are
; a limited resource in PLDs
;













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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996


; SUM THE LOW-ORDER WORD
;

;
; the first 5 bits [0..4] of the low-order word
;
q[0]    := (q[0] :+: (ip_add * dl[0]) :+: cy[15])

q[1]    := (q[1] :+: (ip_add * dl[1]) :+:
        ((ip_add *
                (q[0] * dl[0] +
                dl[0] * cy[15])) +
        (q[0] * cy[15])))

q[2]    := (q[2] :+: (ip_add * dl[2]) :+:
        ((ip_add *
                (q[1] * dl[1] +
                 q[1] *  q[0] *  dl[0] +
                dl[1] *  q[0] *  dl[0] +
                 q[1] * dl[0] * cy[15] +
                dl[1] * dl[0] * cy[15] +
                dl[1] *  q[0] * cy[15])) +
        (q[1] * q[0] * cy[15])))

cy[2]   := ((ip_add *
                (q[2] * dl[2] +
                 q[2] *  q[1] * dl[1] +
                dl[2] *  q[1] * dl[1] +
                 q[2] *  q[1] *  q[0] *  dl[0] +
                 q[2] * dl[1] *  q[0] *  dl[0] +
                dl[2] *  q[1] *  q[0] *  dl[0] +
                dl[2] * dl[1] *  q[0] *  dl[0] +
                 q[2] *  q[1] * dl[0] * cy[15] +
                 q[2] * dl[1] *  q[0] * cy[15] +
                 q[2] * dl[1] * dl[0] * cy[15] +
                dl[2] *  q[1] *  q[0] * cy[15] +
                dl[2] *  q[1] * dl[0] * cy[15] +
                dl[2] * dl[1] *  q[0] * cy[15] +
                dl[2] * dl[1] * dl[0] * cy[15])) +
        (q[2] * q[1] * q[0] * cy[15]))

q[3]    := (q[3] :+: (ip_add * dl[3]) :+: cy[2])

q[4]    := (q[4] :+: (ip_add * dl[4]) :+:
        ((ip_add *
                (q[3] * dl[3] +
                dl[3] * cy[2])) +
        (q[3] * cy[2])))



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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996


;
; the next 3 bits [5..7] of the low-order word
;
q[5]    := (q[5] :+: (ip_add * dl[5]) :+:
        ((ip_add *
                (q[4] * dl[4] +
                 q[4] *  q[3] * dl[3] +
                dl[4] *  q[3] * dl[3] +
                 q[4] * dl[3] * cy[2] +
                dl[4] * dl[3] * cy[2] +
                dl[4] *  q[3] * cy[2])) +
        (q[4] * q[3] * cy[2])))

cy[5]   := ((ip_add * (
                 q[5] * dl[5] +
                 q[5] *  q[4] * dl[4] +
                dl[5] *  q[4] * dl[4] +
                 q[5] *  q[4] *  q[3] * dl[3] +
                 q[5] * dl[4] *  q[3] * dl[3] +
                dl[5] *  q[4] *  q[3] * dl[3] +
                dl[5] * dl[4] *  q[3] * dl[3] +
                 q[5] *  q[4] * dl[3] * cy[2] +
                 q[5] * dl[4] *  q[3] * cy[2] +
                 q[5] * dl[4] * dl[3] * cy[2] +
                dl[5] *  q[4] *  q[3] * cy[2] +
                dl[5] *  q[4] * dl[3] * cy[2] +
                dl[5] * dl[4] *  q[3] * cy[2] +
                dl[5] * dl[4] * dl[3] * cy[2])) +
        (q[5] * q[4] * q[3] * cy[2]))

q[6]    := (q[6] :+: (ip_add * dl[6]) :+: cy[5])

q[7]    := (q[7] :+: (ip_add * dl[7]) :+:
        ((ip_add *
                (q[6] * dl[6] +
                dl[6] * cy[5])) +
        (q[6] * cy[5])))

cy[7]   := ((ip_add *
                (q[7] * dl[7] +
                 q[7] *  q[6] * dl[6] +
                dl[7] *  q[6] * dl[6] +
                 q[7] * dl[6] * cy[5] +
                dl[7] * dl[6] * cy[5] +
                dl[7] *  q[6] * cy[5])) +
        (q[7] * q[6] * cy[5]))





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RFC 1936    Implementing the Internet Checksum in Hardware    April 1996