📄 tablepic.h
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/* machine specific global variables */
int Cpu = PIC84; /* CPU type default */
int RETLW_inst = 0x800; /* RETLW op code (for .byte) */
int Skcycles = 0; /* # of cycles if skipped */
int Vdef = 0; /* defined default V register value */
int Skip_inst = 0; /* current instruction may be skipped */
int Skip_GEN = 0; /* current instruction may generate a skip */
/* opcode classes for 78c10 */
#define GEN 0 /* GENERAL INSTRUCTION f,d */
#define GOTO 1 /* GOTO INSTR (extra cycle) */
#define IMPL 2 /* IMPLIED OPERAND */
#define BIT 3 /* BIT TEST/BRANCH */
#define BSKP 4 /* BIT SKIP */
#define SKP 5 /* SKIP */
#define F_REG 6 /* File only */
#define TRIS 7 /* TRIS instruction */
#define RETLW 8 /* RETLW */
#define CALL 9 /* CALL */
#define LITW 10 /* literal W */
#define IBSKP 11 /* Implied bit skip (SKPC)etc */
#define BBRA 12 /* Bit Branch (compound instr) add a jmp */
/* these instructions should realy be macros */
#define ADDCF 13 /* ADDCF / SUBCF (compound) add SKPNC */
#define ADDDCF 14 /* ADDDCF / SUBDCF (compound) add SKPNDC */
#define NEGF 15 /* Dual instr. NEGF INCF */
#define LCALL 16 /* ADDDCF / SUBDCF (compound) add SKPNDC */
#define NEW71 19 /* New for 16c71 */
#define LIT71 20 /* New literal for 16c71 */
#define F_SKP 21 /* File-only skip -- needs timing fix */
#define PSEUDO 25 /* PSEUDO OP */
/***************************************************************
due to the massive convolutions of the 78c10 instruction set,
the base Opcode is really the index into the opcode parse table.
valid parse entrys are between this number and the first valid entry
for the next instruction.
***************************************************************/
/* Bitmap for valid processors */
#define P5X 1
#define P7X 2
#define P17 4
#define MORE 128
struct oper table[] = {
/* Opcode Class Opcode# t(reused: Bitmap of VALID PROCESSORS)
------ ----- ----- --------- */
"addlw", LIT71, 0x3E00, P7X+MORE,
"addlw ", LIT71, 0xb100, P17,
"addwf", GEN, 0x1C0 , P5X|P7X|P17,
"addwc", GEN, 0x1000 , P17,
"andlw", LITW, 0xE00 , P5X+MORE,
"andlw ", LITW, 0x3900, P7X+MORE,
"andlw ", LITW, 0xb500, P17,
"andwf", GEN, 0x140 , P5X|P7X|P17,
"bc", BBRA, 0x600|(0<<5)|3, P5X+MORE, /* for convenience */
"bc ", BBRA, 0x1800|(0<<7)|3, P7X+MORE, /* for convenience */
"bc ", BBRA, 0x9800|(0<<8)|4, P17, /* for convenience */
"bcf", BIT, 0x400 , P5X|P7X+MORE,
"bcf ", BIT, 0x8800 , P17,
"bdc", BBRA, 0x600|(1<<5)|3, P5X+MORE, /* for convenience */
"bdc ", BBRA, 0x1800|(1<<7)|3, P7X+MORE, /* for convenience */
"bdc ", BBRA, 0x9800|(1<<8)|4, P17, /* for convenience */
"bnc", BBRA, 0x700|(0<<5)|3, P5X+MORE, /* for convenience */
"bnc ", BBRA, 0x1800|(0<<7)|3, P7X+MORE, /* for convenience */
"bnc ", BBRA, 0x9000|(0<<8)|4, P17, /* for convenience */
"bndc", BBRA, 0x700|(1<<5)|3, P5X+MORE, /* for convenience */
"bndc ", BBRA, 0x1800|(1<<7)|3, P7X+MORE, /* for convenience */
"bndc ", BBRA, 0x9000|(1<<8)|4, P17, /* for convenience */
"bnz", BBRA, 0x700|(2<<5)|3, P5X|P7X+MORE, /* for convenience */
"bnz ", BBRA, 0x700|(2<<7)|3, P5X|P7X+MORE, /* for convenience */
"bnz ", BBRA, 0x700|(2<<8)|3, P17, /* for convenience */
"bsf", BIT, 0x500 , P5X|P7X+MORE,
"bsf ", BIT, 0x8000 , P17,
"btfsc", BSKP, 0x600 , P5X|P7X+MORE,
"btfsc ", BSKP, 0x9800 , P17,
"btfss", BSKP, 0x700 , P5X|P7X+MORE,
"btfss ", BSKP, 0x9000 , P17,
"btg", BIT, 0x3800, P17,
"bz", BBRA, 0x600|(2<<5)|3, P5X|P7X+MORE, /* for convenience */
"bz ", BBRA, 0x1800|(2<<7)|3, P7X+MORE, /* for convenience */
"bz ", BBRA, 0x9800|(2<<8)|4, P5X|P7X, /* for convenience */
"call", CALL, 0x900 , P5X+MORE,
"call ", CALL, 0x2000, P7X+MORE,
"call ", CALL, 0xE000, P17,
"clrc", IMPL, 0x403 , P5X+MORE, /* for convenience */
"clrc ", IMPL, 0x1003 , P7X+MORE, /* for convenience */
"clrc ", IMPL, 0x8804 , P17, /* for convenience */
"clrdc", IMPL, 0x423 , P5X+MORE, /* for convenience */
"clrdc ", IMPL, 0x1083 , P7X+MORE, /* for convenience */
"clrdc ", IMPL, 0x8904 , P17, /* for convenience */
"clrf", F_REG, 0x060 , P5X|P7X+MORE,
"clrf ", GEN, 0x2800 , P17, /* diff syntax on 17c42 */
"clrw", IMPL, 0x040 , P5X|P7X+MORE,
"clrw ", IMPL, 0x290A , P17, /* force missing instr */
"clrwdt", IMPL, 0x004 , P5X+MORE,
"clrwdt ", IMPL, 0x064 , P7X+MORE,
"clrwdt ", IMPL, 0x004 , P17,
"clrz", IMPL, 0x443 , P5X+MORE, /* for convenience */
"clrz ", IMPL, 0x1103 , P7X+MORE, /* for convenience */
"clrz ", IMPL, 0x8A04 , P17, /* for convenience */
"comf", GEN, 0x240 , P5X|P7X|P17,
"daw", GEN, 0x2E00 , P17,
"dcfsnz", SKP, 0x2600 , P17,
"decf", GEN, 0x0C0 , P5X|P7X|P17,
"decfsz", SKP, 0x2C0 , P5X|P7X|P17,
"goto", GOTO, 0xA00 , P5X|P7X+MORE,
"goto ", GOTO, 0xC000 , P17,
"incf", GEN, 0x280 , P5X|P7X|P17,
"incfsz", SKP, 0x3C0 , P5X|P7X|P17,
"infsnz", SKP, 0x2400 , P17,
"iorlw", LITW, 0xD00 , P5X+MORE,
"iorlw ", LITW, 0x3800, P7X+MORE,
"iorlw ", LITW, 0xB300, P17,
"iorwf", GEN, 0x100 , P5X|P7X|P17,
"lcall", LITW, 0xB800 , P17, /* timing needs fixing!*/
"movf", GEN, 0x200 , P5X|P7X, /* not on 17C42! */
"movfw", F_REG, 0x200 , P5X|P7X+MORE, /* for convenience */
"movfw ", F_REG, 0x6A00 , P17, /* fake-it on 17c42 */
"movlb", LITW, 0xB800 , P17,
"movlw", LITW, 0xC00 , P5X|P7X+MORE,
"movlw ", LITW, 0xb000 , P5X|P7X,
"movwf", F_REG, 0x020 , P5X|P7X|P17,
"negw", GEN, 0x2C00 , P17,
"nop", IMPL, 0x000 , P5X|P7X|P17,
"option", IMPL, 0x002 , P5X+MORE,
"option ", IMPL, 0x062 , P7X,
"retfie", NEW71, 0x009 , P7X+MORE,
"retfie ", NEW71, 0x005 , P17,
"retlw", RETLW, 0x800 , P5X+MORE,
"retlw ", RETLW, 0x3400, P7X+MORE,
"retlw ", RETLW, 0xB600, P17,
"return", NEW71, 0x008 , P7X+MORE,
"return ", NEW71, 0x002 , P17,
"rlcf", GEN, 0x340 , P5X|P7X|P17, /* 17c syntax */
"rlf", GEN, 0x340 , P5X|P7X|P17,
"rlncf", GEN, 0x2200 , P17,
"rrcf", GEN, 0x300 , P5X|P7X|P17, /* 17c syntax */
"rrf", GEN, 0x300 , P5X|P7X|P17,
"rrncf", GEN, 0x2000 , P17,
"setc", IMPL, 0x503 , P5X+MORE, /* for convenience */
"setc ", IMPL, 0x1403 , P7X+MORE, /* for convenience */
"setc ", IMPL, 0x8004 , P17, /* for convenience */
"setdc", IMPL, 0x523 , P5X+MORE, /* for convenience */
"setdc ", IMPL, 0x1483 , P7X+MORE, /* for convenience */
"setdc ", IMPL, 0x8103 , P17, /* for convenience */
"setf", GEN, 0x2a00 , P17,
"setz", IMPL, 0x543 , P5X+MORE, /* for convenience */
"setz ", IMPL, 0x1503 , P7X+MORE, /* for convenience */
"setz ", IMPL, 0x8203 , P17, /* for convenience */
"skpc", IBSKP, 0x700|(0<<5)|3, P5X+MORE, /* for convenience */
"skpc ", IBSKP, 0x1c00|(0<<7)|3, P7X+MORE, /* for convenience */
"skpc ", IBSKP, 0x9000|(0<<8)|4, P17, /* for convenience */
"skpdc", IBSKP, 0x700|(1<<5)|3, P5X+MORE, /* for convenience */
"skpdc ", IBSKP, 0x1c00|(1<<7)|3, P7X+MORE, /* for convenience */
"skpdc ", IBSKP, 0x9000|(1<<8)|4, P17, /* for convenience */
"skpnc", IBSKP, 0x600|(0<<5)|3, P5X+MORE, /* for convenience */
"skpnc ", IBSKP, 0x1800|(0<<7)|3, P7X+MORE, /* for convenience */
"skpnc ", IBSKP, 0x9800|(0<<8)|4, P17, /* for convenience */
"skpndc", IBSKP, 0x600|(1<<5)|3, P5X+MORE, /* for convenience */
"skpndc ", IBSKP, 0x1800|(1<<7)|3, P7X+MORE, /* for convenience */
"skpndc ", IBSKP, 0x9800|(1<<8)|4, P17, /* for convenience */
"skpnz", IBSKP, 0x600|(2<<5)|3, P5X+MORE, /* for convenience */
"skpnz ", IBSKP, 0x1800|(2<<7)|3, P7X+MORE, /* for convenience */
"skpnz ", IBSKP, 0x9800|(2<<8)|4, P17, /* for convenience */
"skpz", IBSKP, 0x700|(2<<5)|3, P5X+MORE, /* for convenience */
"skpz ", IBSKP, 0x1c00|(2<<7)|3, P7X+MORE, /* for convenience */
"skpz ", IBSKP, 0x9000|(2<<8)|4, P17, /* for convenience */
"sleep", IMPL, 0x003 , P5X+MORE,
"sleep ", IMPL, 0x063 , P7X+MORE,
"sleep ", IMPL, 0x003 , P17,
"sublw", LIT71, 0x3c00, P5X|P7X+MORE,
"sublw ", LIT71, 0xB200, P17,
"subwf", GEN, 0x080 , P5X|P7X|P17,
"subwfb", GEN, 0x0200 , P17,
"swapf", GEN, 0x380 , P5X|P7X|P17,
"tris", TRIS, 0x000 , P5X+MORE,
"tris ", TRIS, 0x060 , P7X, /* NOT ON 17 */
"tstf", F_REG, 0x220 , P5X|P7X, /* NOT ON 17 */
"tstfsz", SKP, 0x3300 , P17, /* d accepted but ignored */
"xorlw", LITW, 0xF00 , P5X+MORE,
"xorlw ", LITW, 0x3a00, P7X+MORE,
"xorlw ", LITW, 0xB400, P17,
"xorwf", GEN, 0x180 , P5X|P7X|P17
};
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