hal_diag.c

ecos实时嵌入式操作系统

/*=============================================================================
//
//      hal_diag.c
//
//      HAL diagnostic output code
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   nickg, gthomas
// Contributors:nickg, gthomas
// Date:        2001-04-23
// Purpose:     HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

#include <pkgconf/hal.h>
#include CYGBLD_HAL_VARIANT_H           // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration

#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_arch.h>           // basic machine info
#include <cyg/hal/hal_intr.h>           // interrupt macros
#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_if.h>             // interface API
#include <cyg/hal/hal_misc.h>           // Helper functions
#include <cyg/hal/ep93xx.h>               // platform definitions

/*---------------------------------------------------------------------------*/

//
// Default the source clock to the UARTs to be 7Mhz
//
#define BAUD_RATE(n) (((14745600)/(16*n))-1)
#define UARTBASE_TO_PORT(n) (((((cyg_uint32)n)>>16)&0x3)+1)
//-----------------------------------------------------------------------------
typedef struct {
    cyg_uint8 *base;
    cyg_int32  msec_timeout;
    int        isr_vector;
} channel_data_t;

static channel_data_t ep9312_ser_channels[] = {
    { (cyg_uint8 *)EP9312_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1 },
    { (cyg_uint8 *)EP9312_UART2, 1000, CYGNUM_HAL_INTERRUPT_UART2 },
    { (cyg_uint8 *)EP9312_UART3, 1000, CYGNUM_HAL_INTERRUPT_UART3 }
};

static void
DisableUART(cyg_uint32 Channel)
{
    cyg_uint32 DevCfg;

    //
    // Enable the clock to the UART
    //
    HAL_READ_UINT32(EP9312_DEVCFG, DevCfg);

    switch (Channel)
    {
        case 1:
        {
            DevCfg &= ~EP9312_DEVCFG_U1EN;
            break;
        }
        case 2:
        {
            DevCfg &= ~EP9312_DEVCFG_U2EN;
            break;
        }
        case 3:
        {
            DevCfg &= ~EP9312_DEVCFG_U3EN;
            break;
        }
        default:
        {
        }
    }
    HAL_WRITE_UINT32(EP9312_DEVCFG, DevCfg);
}

static void
EnableUART(cyg_uint32 Channel)
{
    cyg_uint32 DevCfg;

    //
    // Enable the clock to the UART
    //
    HAL_READ_UINT32(EP9312_DEVCFG, DevCfg);

    switch (Channel)
    {
        case 1:
        {
            DevCfg |= EP9312_DEVCFG_U1EN;
            break;
        }
        case 2:
        {
            DevCfg |= EP9312_DEVCFG_U2EN;
            break;
        }
        case 3:
        {
            DevCfg |= EP9312_DEVCFG_U3EN;
            break;
        }
        default:
        {
        }
    }
    HAL_WRITE_UINT32(EP9312_DEVCFG, DevCfg);
}


//-----------------------------------------------------------------------------

static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint32 baud;
    
    DisableUART(UARTBASE_TO_PORT(base));
    
    // 
    // Disable while configuring
    //
    HAL_WRITE_UINT32(base+EP9312_UART_CR, 0);
    HAL_WRITE_UINT32(base+EP9312_UART_MCR, 0);
    HAL_WRITE_UINT32(base+EP9312_UART_SR, 0);

    //
    // Set the baud rate.
    //
    baud = BAUD_RATE(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
    HAL_WRITE_UINT32(base+EP9312_UART_LCR_L, baud & 0xFF);
    HAL_WRITE_UINT32(base+EP9312_UART_LCR_M, baud >> 8);

    // 
    // 8bits - 1 stop bit - no parity.
    //
    HAL_WRITE_UINT32(base+EP9312_UART_LCR_H, EP9312_UART_LCR_H_FE | 
        EP9312_UART_LCR_H_WLEN8);

    // 
    // Enable
    //
    HAL_WRITE_UINT32(base+EP9312_UART_CR, EP9312_UART_CR_UARTE);

    EnableUART(UARTBASE_TO_PORT(base));
}

void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint32 status;

    do {
        HAL_READ_UINT32(base+EP9312_UART_FR, status);
    } while ((status & EP9312_UART_FR_TXFF) != 0);

    HAL_WRITE_UINT32(base+EP9312_UART_DATA, c);
}

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint32 status;
    cyg_uint32 c;

    HAL_READ_UINT32(base+EP9312_UART_FR, status);
    if ((status & EP9312_UART_FR_RXFE) != 0)
        return false;

    HAL_READ_UINT32(base+EP9312_UART_DATA, c);
    *ch = c;

    return true;
}

cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
    cyg_uint8 ch;

    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
    return ch;
}

static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
                         cyg_uint32 __len)
{
    while(__len-- > 0)
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
}

static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
    while(__len-- > 0)
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
}

cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
    int delay_count;
    channel_data_t* chan = (channel_data_t*)__ch_data;
    cyg_bool res;

    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps

    for(;;) {
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
        if (res || 0 == delay_count--)
            break;
        
        CYGACC_CALL_IF_DELAY_US(100);
    }
    return res;
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
#if 0
    static int irq_state = 0;
#endif
    channel_data_t* chan = (channel_data_t*)__ch_data;
    int ret = 0;
    CYGARC_HAL_SAVE_GP();

    switch (__func) {
#if 0
    case __COMMCTL_IRQ_ENABLE:
        irq_state = 1;

        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
        HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);

        HAL_INTERRUPT_UNMASK(chan->isr_vector);
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = irq_state;
        irq_state = 0;

        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);

        HAL_INTERRUPT_MASK(chan->isr_vector);
        break;
#endif
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = chan->isr_vector;