sdramcfg.h

ecos实时嵌入式操作系统

/*=============================================================================
//
//      sdramcfg.h
//
//      SDRAM Configuration Routine.
//
//=============================================================================
//####COPYRIGHTBEGIN####
//
// -------------------------------------------
// Copyright(c) Cirrus Logic Corporation 2003, All Rights Reserved
// -------------------------------------------
//
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jordan
// Contributors: rgorsegn
// Date:         2003-08-15
// Purpose:      Cirrus Logic EP93xx SDRAM Config Routine
// Description: 
// Usage:        #include <cyg/hal/sdramcfg.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

#define GLOBALCFG_INIT                       0x00000001
#define GLOBALCFG_MRS                        0x00000002
#define GLOBALCFG_SMEMBUSY                   0x00000020
#define GLOBALCFG_LCR                        0x00000040
#define GLOBALCFG_REARBEN                    0x00000080
#define GLOBALCFG_CLKSHUTDOWN                0x40000000
#define GLOBALCFG_CKE                        0x80000000

#define REFRESH_MASK                         0x0000FFFF

#define BOOTSTATUS_WIDTH_32                  0x00000002
#define BOOTSTATUS_WIDTH_16                  0x00000001
#define BOOTSTATUS_WIDTH_8                   0x00000000
#define BOOTSTATUS_WIDTH_MASK                0x00000003
#define BOOTSTATUS_MEDIA                     0x00000004

#define DEVCFG_EXTBUSWIDTH                   0x00000004
#define DEVCFG_BANKCOUNT                     0x00000008
#define DEVCFG_SROM512                       0x00000010
#define DEVCFG_SROMLL                        0x00000020
#define DEVCFG_2KPAGE                        0x00000040
#define DEVCFG_SFCONFIGADDR                  0x00000080
#define DEVCFG_CASLAT_MASK                   0x00070000
#define DEVCFG_CASLAT_2                      0x00010000
#define DEVCFG_CASLAT_3                      0x00020000
#define DEVCFG_CASLAT_4                      0x00030000
#define DEVCFG_CASLAT_5                      0x00040000
#define DEVCFG_CASLAT_6                      0x00050000
#define DEVCFG_CASLAT_7                      0x00060000
#define DEVCFG_CASLAT_8                      0x00070000
#define DEVCFG_WBL                           0x00080000
#define DEVCFG_RASTOCAS_MASK                 0x00300000
#define DEVCFG_RASTOCAS_2                    0x00200000
#define DEVCFG_RASTOCAS_3                    0x00300000
#define DEVCFG_AUTOPRECHARGE                 0x01000000

//****************************************************************************
// Delay200 - Delays200 us
//
//   Uses    r0
//****************************************************************************
    .macro Delay200
    mov     r0, #64
200:
    subs    r0, r0, #1
    bne     200b
    .endm
        
    .macro SdramCfg
	//
    // Initialize the SDRAM Configuration
    //
#ifdef HAL_PLATFORM_EP9301
	ldr     r0, =(DEVCFG_BANKCOUNT | DEVCFG_SROMLL | DEVCFG_CASLAT_3 | \
                  DEVCFG_RASTOCAS_3 | DEVCFG_EXTBUSWIDTH)
#else
	ldr     r0, =(DEVCFG_BANKCOUNT | DEVCFG_SROMLL | DEVCFG_CASLAT_2 | \
                  DEVCFG_RASTOCAS_2)
#endif // HAL_PLATFORM_EP9301
    ldr     r1, =0x8006001C
    str     r0, [r1]

    Delay200

    //
    // Set the Initialize and MRS bits (issue continuous NOP commands
    // (INIT & MRS set))
    //
    ldr     r0, =(GLOBALCFG_INIT | GLOBALCFG_MRS | GLOBALCFG_CKE)
    ldr     r1, =0x80060004
    str     r0, [r1]

    Delay200

    //
    // Clear the MRS bit to issue a precharge all.
    //
    ldr     r0, =(GLOBALCFG_INIT | GLOBALCFG_CKE)
    str     r0, [r1]

    //
    // Temporarily set the refresh timer to 0x10.  Make it really low so that
    // auto refresh cycles are generated. is refreshed.
    //
    ldr     r0, =0x10
    ldr     r1, =0x80060008
    str     r0, [r1]

    Delay200

#ifdef HAL_PLATFORM_EP9301
    ldr     r0, =0x204
#else
    ldr     r0, =0x23
#endif // HAL_PLATFORM_EP9301
    ldr     r1, =0x80060008
    str     r0, [r1]

    //
    // Select mode register update mode
    //
    ldr     r0, =(GLOBALCFG_CKE | GLOBALCFG_MRS)
    ldr     r1, =0x80060004
    str     r0, [r1]

// *******************************************************************
//
// Program the SDRAM mode register using the row information.
//
//       |           |           |           |
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |13|12|11|10|09|08|07|06|05|04|03|02|01|00|
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+
//   +---------+------+  +---+--+  +   +--+--+
//              |             |     |     |
//          Must Be Zero      |     |     |
//                            |     |     |
//                            |     |     |
//    LTMODE   ---------------+     |     |
//                                  |     |
//  Wrap type  ---------------------+     |
//                                        |
// CAS Latency ---------------------------+
//
// *******************************************************************
//
// Row Column mapping for 256Meg X 16 Bits X 2.
//
//           B1  B0  A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
//
// Row/Bank  A27 A26 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 
//
// Col       A27 A26             AP  A25 A24 A09 A08 A07 A06 A05 A04 A03 A02 
//
// *******************************************************************
// Sets all four banks using  - Cas latency 3 
//                            - Wrap type sequential
//                            - Burst Length 4 
//
// *******************************************************************
#ifdef HAL_PLATFORM_EP9301
    mov     r1, #0x0006600
    ldr     r0, [r1]
#else
    mov     r1, #0x0008800
    ldr     r0, [r1]

    ldr     r1, =0x0400000
    ldr     r0, [r1]

    ldr     r1, =0x0808800
    ldr     r0, [r1]

    ldr     r1, =0x0c08800
    ldr     r0, [r1]
#endif // HAL_PLATFORM_EP9301

    //
    // Select mode register update mode
    //
    ldr     r0, =GLOBALCFG_CKE
    ldr     r1, =0x80060004
    str     r0, [r1]

    .endm