📄 pmx.h
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//***************************************************************************/
//*
//* Copyright (c) 1998-99 Intel Corporation.
//* All rights reserved.
//*
//*
//***************************************************************************/
//////////////////////////////////////////////////////////////////////////////
// Module Name: PMX.h
// Abstract: Exteral/Internal header file for PMX.c and pmxdll.c
//
//////////////////////////////////////////////////////////////////////////////
#ifndef __PMX_H__
#define __PMX_H__
//////////////////////////////////////////////////////////////////////////////
// INCLUDES & DEFINES
//////////////////////////////////////////////////////////////////////////////
#include "myver.h"
#include "ui64.h"
#include "cpuid32.h"
#include "error32.h"
#define MAX_NUM_PROCESSORS 31
// Control2 Register Bits
#define CR0_PE 0x00000001 // bit0 Protection Enable
#define CR0_MP 0x00000002 // bit1 Monitor Coprocessor
#define CR0_EM 0x00000004 // bit2 Emulation
#define CR0_TS 0x00000008 // bit3 Task Switched
#define CR0_ET 0x00000010 // bit4 Extension Type
#define CR0_NE 0x00000020 // bit5 Numeric Error
#define CR0_WP 0x00010000 // bit16 Write Protect
#define CR0_AM 0x00040000 // bit18 Alignment Mask
#define CR0_NW 0x20000000 // bit29 Not Write-through
#define CR0_CD 0x40000000 // bit30 Cache Disable
#define CR0_PG 0x80000000 // bit31 Paging
#define CR3_PWT 0x00000008 // bit3 Page-level Writes Transparent
#define CR3_PCD 0x00000010 // bit4 Page-level Cache Disable
#define CR3_PAGE_DIR_BASE 0xFFFFF000 // bits13-31 Page Direcectory Base
#define CR4_VME 0x00000001 // bit0 Virtual-8086 Mode extensions
#define CR4_PVI 0x00000002 // bit1 Protected-Mode Virtual Interrupts
#define CR4_TSD 0x00000004 // bit2 Time Stamp Disable
#define CR4_DE 0x00000008 // bit3 Debug Extensions
#define CR4_PSE 0x00000010 // bit4 Page Size Extensions
#define CR4_PAE 0x00000020 // bit5 Physical Address Entension
#define CR4_MCE 0x00000040 // bit6 Machine Check Enable
#define CR4_PGE 0x00000080 // bit7 Page Global Enable
#define CR4_PCE 0x00000100 // bit8 Performance-Montioring Counter Enable (RDPMC enable)
// Debug Register Bits
#define DR6_B0 0x00000001 // bit0 DR0 Break Occurred
#define DR6_B1 0x00000002 // bit1 DR1 Break Occurred
#define DR6_B2 0x00000004 // bit2 DR2 Break Occurred
#define DR6_B3 0x00000008 // bit3 DR3 Break Occurred
#define DR6_BD 0x00002000 // DR0-DR7 access detected
#define DR6_BS 0x00004000 // Single Step Break detected
#define DR6_BT 0x00008000 // Task Switch Break detected
#define DR7_L0 0x00000001 // DR0 Local Task Enable
#define DR7_G0 0x00000002 // DR0 Global Task Enable
#define DR7_L1 0x00000004 // DR1 Local Task Enable
#define DR7_G1 0x00000008 // DR1 Global Task Enable
#define DR7_L2 0x00000010 // DR2 Local Task Enable
#define DR7_G2 0x00000020 // DR2 Global Task Enable
#define DR7_L3 0x00000040 // DR3 Local Task Enable
#define DR7_G3 0x00000080 // DR3 Global Task Enable
#define DR7_LE 0x00000100 // Exact Local Breakpoints (Not implemented on Pentium(r) Pro processor)
#define DR7_GE 0x00000200 // Exact Global Breakpoints (Not implemented on Pentium(r) Pro processor)
#define DR7_GD 0x00002000 // Enable Breaks on DR0-DR7 access
#define DR7_COND0 0x000F0000 // Mask for DR0 Break Condition
#define DR7_RW0 0x00030000 // Mask for DR0 Read/Write/Execute/IO Condition
#define DR7_LEN0 0x000C0000 // Mask for DR0 Break Condition Length
#define DR7_COND0_SHIFT 16 // Bit shift for DR0 Break Condition
#define DR7_COND1 0x00F00000 // Mask for DR1 Break Condition
#define DR7_RW1 0x00300000 // Mask for DR1 Read/Write/Execute/IO Condition
#define DR7_LEN1 0x00C00000 // Mask for DR1 Break Condition Length
#define DR7_COND1_SHIFT 20 // Bit shift for DR1 Break Condition
#define DR7_COND2 0x0F000000 // Mask for DR2 Break Condition
#define DR7_RW2 0x03000000 // Mask for DR2 Read/Write/Execute/IO Condition
#define DR7_LEN2 0x0C000000 // Mask for DR2 Break Condition Length
#define DR7_COND2_SHIFT 24 // Bit shift for DR2 Break Condition
#define DR7_COND3 0xF0000000 // Mask for DR3 Break Condition
#define DR7_RW3 0x30000000 // Mask for DR3 Read/Write/Execute/IO Condition
#define DR7_LEN3 0xC0000000 // Mask for DR3 Break Condition Length
#define DR7_COND3_SHIFT 28 // Bit shift for DR3 Break Condition
// IDT Entry Bits
#define IDT_TYPE 0x00001F00
#define IDT_TRAPGATE16 0x00000700
#define IDT_TRAPGATE32 0x00000F00
#define IDT_INTERRUPTGATE16 0x00000600
#define IDT_INTERRUPTGATE32 0x00000E00
#define IDT_TASKGATE 0x00000500
#define IDT_OFFSET15_0 0x0000FFFF
#define IDT_OFFSET31_16 0xFFFF0000
#define IDT_SELECTOR 0xFFFF0000
#define IDT_SELECTOR_SHIFT 16
#define IDT_P 0x00008000
#define IDT_DPL 0x00006000
#define IDT_DPL_SHIFT 13
// Segment Descriptor bits
#define SEL_BASE_31_24 0xFF000000 // bit63-56 Base 31:24
#define SEL_G 0x00800000 // bit55 Granularity
#define SEL_D 0x00400000 // bit54 Default Operation size
#define SEL_0 0x00200000 // bit53 Reserved = 0
#define SEL_AVL 0x00100000 // bit52 Available
#define SEL_LIMIT_19_16 0x000F0000 // bit51-48 Limit 19:16
#define SEL_P 0x00008000 // bit47 Present
#define SEL_DPL 0x00006000 // bit46,45 DPL
#define SEL_S 0x00001000 // bit44 System/User
#define SEL_TYPE 0x00000F00 // bit43-40 Type
#define SEL_BASE_23_16 0x000000FF // bit39-32 Base 23:16
#define SEL_BASE_15_0 0xFFFF0000 // bit15-0 Base 15:0
#define SEL_LIMIT_15_0 0x0000FFFF // bit15-0 Limit 15:0
#define SEL_DPL_SHIFT 13
#define SEL_TYPE_SHIFT 8
#define SEL_CD 0x00000800 // bit43
#define SEL_C_C 0x00000400 // bit42
#define SEL_C_R 0x00000200 // bit41
#define SEL_C_A 0x00000100 // bit40
#define SEL_D_E 0x00000400 // bit42
#define SEL_D_R 0x00000200 // bit41
#define SEL_D_A 0x00000100 // bit40
#define PAGE_P 0x000000001 // bit0 Present
#define PAGE_RW 0x000000002 // bit1 Read/Write
#define PAGE_US 0x000000004 // bit2 Usr/Super
#define PAGE_PWT 0x000000008 // bit3 Write-Through
#define PAGE_PCD 0x000000010 // bit4 Cache Disable
#define PAGE_A 0x000000020 // bit5 Accessed
#define PAGE_D 0x000000040 // bit6 Dirty
#define PAGE_PS 0x000000080 // bit7 Reserved
#define PAGE_G 0x000000100 // bit8 Global page
#define PAGE_AVAIL 0x000000E00 // bit9-11 OS Available
#define PAGE_4K_BASE_ADDR 0xFFFFFF000 // bit31-12 PTE 4K Page Base Address
#define PAGE_4M_BASE_ADDR 0x3FF000000 // bit31-22 PDE 4M Page Base Address
// ID Strings for module versions
// these should be the first characters of
// the module string and can be used to
// identify individual module for version
// information
#define PMXDLL_ID_STR "pmxdll.dll"
#define IDRVDLL_ID_STR "idrvdll.dll"
#define PMXDRVSYS_ID_STR "pmxdrv.sys"
#define PMXDRVVXD_ID_STR "pmxdrv.vxd"
typedef struct {
WORD wOffset15_0;
WORD wSelector;
WORD wAttributes;
WORD wOffset31_16;
} IDT_t;
typedef struct {
WORD wLimit15_0;
WORD wBase15_0;
DWORD dwTheRest;
} SEL_t;
typedef struct {
DWORD dwSize;
DWORD dwProcessorMask;
DWORD dwSuccessMask;
union {
UINT uiReg64;
UINT uiIDT;
UINT uiMSR;
UINT uiSEL;
};
union {
UINT64 ui64AndMask;
IDT_t IDTAndMask;
SEL_t SELAndMask;
};
union {
UINT64 ui64OrMask;
IDT_t IDTOrMask;
SEL_t SELOrMask;
};
union {
UINT64 ui64OldValue[MAX_NUM_PROCESSORS+1];
IDT_t IDTOldValue[MAX_NUM_PROCESSORS+1];
SEL_t SELOldValue[MAX_NUM_PROCESSORS+1];
};
union {
UINT64 ui64RetValue[MAX_NUM_PROCESSORS+1];
IDT_t IDTRetValue[MAX_NUM_PROCESSORS+1];
SEL_t SELRetValue[MAX_NUM_PROCESSORS+1];
};
} PMX_REG64_t;
typedef PMX_REG64_t *PPMX_REG64_t;
typedef struct {
DWORD dwSize;
DWORD dwProcessorMask;
DWORD dwSuccessMask;
UINT uiReg32;
UINT uiAndMask;
UINT uiOrMask;
UINT uiOldValue[MAX_NUM_PROCESSORS+1];
UINT uiRetValue[MAX_NUM_PROCESSORS+1];
} PMX_REG32_t;
typedef PMX_REG32_t *PPMX_REG32_t;
typedef struct {
DWORD dwSize;
DWORD dwSrc;
DWORD dwDest;
UINT uiLength;
DWORD dwFlags;
} PMX_STR_t;
typedef PMX_STR_t *PPMX_STR_t;
typedef struct {
DWORD dwSize;
DWORD dwPhysAddr;
DWORD dwNumPages;
PVOID pvVirtAddr;
} PMX_MAPPHYS_t;
typedef PMX_MAPPHYS_t *PPMX_MAPPHYS_t;
typedef struct {
DWORD dwSize;
DWORD dwPhysAddr;
DWORD dwNumPages;
PVOID pvVirtAddr;
DWORD dwFlags; // Flags
DWORD dwAlign; // Alignment for allocating
DWORD dwPhysMin; // Min allowable Physical addr for allocating
DWORD dwPhysMax; // Max allowable Physical addr for allocating
} PMX_ALLOCATEPHYS_t;
typedef PMX_ALLOCATEPHYS_t *PPMX_ALLOCATEPHYS_t;
typedef struct {
DWORD dwSize;
PVOID pvVirtAddr;
DWORD dwNumPages;
DWORD dwFlags;
} PMX_LINLOCK_t;
typedef PMX_LINLOCK_t *PPMX_LINLOCK_t;
typedef struct {
DWORD dwSize; // sizeof(PMX_PAGE_t)
PVOID pvVirtAddr; // Linear address for which you want to read/write page tables
DWORD dwPDEAndMask; // Page Directory Entry AND mask used for writting
DWORD dwPDEOrMask; // Page Directory Entry OR mask used for writting
DWORD dwPTEAndMask; // Page Table Entry AND mask used for writting
DWORD dwPTEOrMask; // Page Table Entry OR mask used for writting
DWORD dwOldPageDirectoryEntry; // Page Directory Entry Before writting
DWORD dwOldPageTableEntry; // Page Table Entry Before writting ( = 0 for 4MB pages)
DWORD dwRetPageDirectoryEntry; // Page Directory Entry After reading/writting
DWORD dwRetPageTableEntry; // Page Table Entry After reading/writting ( = 0 for 4MB pages)
} PMX_PAGE_t;
typedef PMX_PAGE_t *PPMX_PAGE_t;
// PMX_IO_t.dwIOType vaules
#define PMX_IO_IN8 1
#define PMX_IO_IN16 2
#define PMX_IO_IN32 3
#define PMX_IO_OUT8 4
#define PMX_IO_OUT16 5
#define PMX_IO_OUT32 6
typedef struct {
DWORD dwSize;
DWORD dwIOType;
UINT uiIOPort;
UINT uiValue;
} PMX_IO_t;
typedef PMX_IO_t *PPMX_IO_t;
// PMX_PCI_t.dwPCIType vaules
#define PMX_PCI_IN8 1
#define PMX_PCI_IN16 2
#define PMX_PCI_IN32 3
#define PMX_PCI_OUT8 4
#define PMX_PCI_OUT16 5
#define PMX_PCI_OUT32 6
typedef struct {
DWORD dwSize;
DWORD dwPCIType;
UINT uiPCICFAddr;
UINT uiAndMask;
UINT uiOrMask;
UINT uiOldValue;
UINT uiRetValue;
} PMX_PCI_t;
typedef PMX_PCI_t *PPMX_PCI_t;
#define PMX_INV_WBINVD 1
#define PMX_INV_INVD 2
#define PMX_INV_INVLPG 3
typedef struct {
DWORD dwSize;
DWORD dwProcessorMask;
DWORD dwSuccessMask;
DWORD dwINVType;
void *pvINVPage;
} PMX_INV_t;
typedef PMX_INV_t *PPMX_INV_t;
typedef struct {
DWORD dwSize;
DWORD dwProcessorMask;
DWORD dwSuccessMask;
CPUID_t cpuidRetValue[MAX_NUM_PROCESSORS+1];
} PMX_CPUID_t;
typedef PMX_CPUID_t *PPMX_CPUID_t;
//////////////////////////////////////////////////////////////////////////////
// FUNCTION PROTOTYPES
//////////////////////////////////////////////////////////////////////////////
#ifdef PMXDLL_INTERNAL
#define PMXAPI __declspec( dllexport )
#else
#define PMXAPI __declspec( dllimport )
#endif
PMXAPI BOOL PMxInit(DEBUG_MSG_LEVEL dml, MYVER_t *pVer);
PMXAPI BOOL PMxDestroy();
PMXAPI DWORD PMxGetLastError(char *, UINT);
PMXAPI BOOL PMxRDMSR(PPMX_REG64_t ppmxReg64);
PMXAPI BOOL PMxWRMSR(PPMX_REG64_t ppmxReg64);
PMXAPI BOOL PMxRDCR(PPMX_REG32_t ppmxReg32);
PMXAPI BOOL PMxWRCR(PPMX_REG32_t ppmxReg32);
PMXAPI BOOL PMxRDDR(PPMX_REG32_t ppmxReg32);
PMXAPI BOOL PMxWRDR(PPMX_REG32_t ppmxReg32);
PMXAPI BOOL PMxIO(PPMX_IO_t ppmxIO);
PMXAPI BOOL PMxPCI(PPMX_PCI_t ppmxPCI);
PMXAPI BOOL PMxINV(PPMX_INV_t ppmxINV);
PMXAPI BOOL PMxRDIDT(PPMX_REG64_t ppmxReg64);
PMXAPI BOOL PMxWRIDT(PPMX_REG64_t ppmxReg64);
PMXAPI BOOL PMxRDSEL(PPMX_REG64_t ppmxReg64);
PMXAPI BOOL PMxWRSEL(PPMX_REG64_t ppmxReg64);
PMXAPI BOOL PMxRDPAGE(PPMX_PAGE_t ppmxPage);
PMXAPI BOOL PMxWRPAGE(PPMX_PAGE_t ppmxPage);
PMXAPI BOOL PMxMapPhys(PPMX_MAPPHYS_t ppmxMapPhys);
PMXAPI BOOL PMxUnmapPhys(PPMX_MAPPHYS_t ppmxMapPhys);
PMXAPI BOOL PMxAllocatePhys(PPMX_ALLOCATEPHYS_t ppmxAllocatePhys);
PMXAPI BOOL PMxFreePhys(PPMX_ALLOCATEPHYS_t ppmxAllocatePhys);
PMXAPI BOOL PMxLinLock(PPMX_LINLOCK_t ppmxLinLock);
PMXAPI BOOL PMxLinUnlock(PPMX_LINLOCK_t ppmxLinLock);
PMXAPI BOOL PMxCPUID(PPMX_CPUID_t ppmxCPUID);
#endif //__PMX_h__
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