8x8.dsp

载dsp上实现16dct和8dct的程序

{  TWO DIMENSIONAL, FAST, DISCRETE COSINE TRANSFORM, 8 x 8 POINTS
  
   Implementation:
        as described by Hsieh S. Hou in IEEE Transactions on Acoustics, 
        Speech, and Signal Processing, Vol. ASSP-35, No. 10, October 1987

   Target Processor:
        ADSP-2100 family of DSP processors from Analog Devices, Inc.

   Execution Benchmark:
        2492 instruction cycles -- ADSP-2101 -- 0.12460 ms at CLKOUT=20.00MHz

   Memory Storage Requirement:
        208 PM = 201 program memory code, 7 program memory data (coefficients)
        16 DM = 8 data memory scratch pad, 8 data memory (8-pt vector)
        Note: resulting transform coefficients written over original input data
        assumes: unsigned 8-bit input data, signed 16-bit output coefficients

   Author of Code:
        Christoph D. Cavigioli -- DSP Applications Engineer -- [phone]

   Release History:
        27-March-1989
        Revised: 23-July-1989
        Revised for ADSP-2101 by Ron Coughlin 28-July-1993

   Analog Devices, Inc., DSP Division, P.O.Box 9106, Norwood, MA 02062, USA
}

.module/ram/abs=0      fast_8x8_dct;
.var/pm/ram            cosvals[15];        { cosine coefficients }
.var/circ/abs=0x3800   tmp[8];             { temporary scratch memory }
.var                   xadr, xadr2;
.var                   x[64];              { 8x8 block to transform }
.global                tmp;
.external  DIF8_8, DIF4_8, DIF2_8, RLR4_8, RLR8_8, DC_AND_BREV_8;
.init      x: <xx.dat>;
.init  cosvals[0]: h#7D8A00, h#471C00, h#E70800, h#959300;
.init  cosvals[4]: h#764100, h#CF0500;
.init  cosvals[6]: h#5A8200;

        jump setup; rti; rti; rti;      { start here on reset } 
        rti; rti; rti; rti;             { irq2 interrupt vector }
        rti; rti; rti; rti;             { sport0 tx interrupt vector }
        rti; rti; rti; rti;             { sport0 rx interrupt vector }
        rti; rti; rti; rti;             { sport1 tx interrupt vector }
        rti; rti; rti; rti;             { sport1 rx interrupt vector }
        rti; rti; rti; rti;             { timer interrupt vector }

setup:  l0=0; l1=0; l2=0; l3=0; l5=0; l6=0; m6=1; se=1;
rows:   si=^x;                  { cols: ^x }
        dm(xadr)=si;
        i2=si;
        si=^x+7;                { cols: ^x+56 }
        dm(xadr2)=si;
        i3=si;
        m5=1;                   { cols: 8 }
        cntr=8;
        do rowdcts until ce;
                i6=^cosvals;
                m2=2;           { cols: 16 }
                m3=-2;          { cols: -16 }
                call DIF8_8;
                call DIF4_8;
                call DIF2_8;
                call RLR4_8;
                call RLR8_8;
                si=dm(xadr);
                i5=si;
                call DC_AND_BREV_8;
nextrow:        ay0=8;          { cols: 1 }
                ax0=dm(xadr);
                ar=ax0+ay0;
                dm(xadr)=ar;
                i2=ar;
                ax0=dm(xadr2);
                ar=ax0+ay0;
                dm(xadr2)=ar;
rowdcts:        i3=ar;
cols:   si=^x;                  { cols: ^x }
        dm(xadr)=si;
        i2=si;
        si=^x+56;               { cols: ^x+56 }
        dm(xadr2)=si;
        i3=si;
        m5=8;                   { cols: 8 }
        cntr=8;
        do coldcts until ce;
                i6=^cosvals;
                m2=16;          { cols: 16 }
                m3=-16;         { cols: -16 }
                call DIF8_8;
                call DIF4_8;
                call DIF2_8;
                call RLR4_8;
                call RLR8_8;
                si=dm(xadr);
                i5=si;
                call DC_AND_BREV_8;
nextcol:        ay0=1;          { cols: 1 }
                ax0=dm(xadr);
                ar=ax0+ay0;
                dm(xadr)=ar;
                i2=ar;
                ax0=dm(xadr2);
                ar=ax0+ay0;
                dm(xadr2)=ar;
coldcts:        i3=ar;
wait3:  idle;
        jump wait3;
.endmod;