intel_mmx.txt

x86 mmx 汇编指令大全

       operand is zero. `PMVNZB' moves if the byte is non-zero. `PMVLZB'
       moves if the byte is less than zero, and `PMVGEZB' moves if the byte
       is greater than or equal to zero.

       Note that these instructions cannot take a register as their second
       source operand.

 A.129 `POR': MMX Bitwise OR

       POR mmxreg,r/m64              ; 0F EB /r             [PENT,MMX]

       `POR' performs a bitwise OR operation between its two operands (i.e.
       each bit of the result is 1 if and only if at least one of the
       corresponding bits of the two inputs was 1), and stores the result
       in the destination (first) operand.

 A.130 `PSLLx', `PSRLx', `PSRAx': MMX Bit Shifts

       PSLLW mmxreg,r/m64            ; 0F F1 /r             [PENT,MMX] 
       PSLLW mmxreg,imm8             ; 0F 71 /6 ib          [PENT,MMX]

       PSLLD mmxreg,r/m64            ; 0F F2 /r             [PENT,MMX] 
       PSLLD mmxreg,imm8             ; 0F 72 /6 ib          [PENT,MMX]

       PSLLQ mmxreg,r/m64            ; 0F F3 /r             [PENT,MMX] 
       PSLLQ mmxreg,imm8             ; 0F 73 /6 ib          [PENT,MMX]

       PSRAW mmxreg,r/m64            ; 0F E1 /r             [PENT,MMX] 
       PSRAW mmxreg,imm8             ; 0F 71 /4 ib          [PENT,MMX]

       PSRAD mmxreg,r/m64            ; 0F E2 /r             [PENT,MMX] 
       PSRAD mmxreg,imm8             ; 0F 72 /4 ib          [PENT,MMX]

       PSRLW mmxreg,r/m64            ; 0F D1 /r             [PENT,MMX] 
       PSRLW mmxreg,imm8             ; 0F 71 /2 ib          [PENT,MMX]

       PSRLD mmxreg,r/m64            ; 0F D2 /r             [PENT,MMX] 
       PSRLD mmxreg,imm8             ; 0F 72 /2 ib          [PENT,MMX]

       PSRLQ mmxreg,r/m64            ; 0F D3 /r             [PENT,MMX] 
       PSRLQ mmxreg,imm8             ; 0F 73 /2 ib          [PENT,MMX]

       `PSxxQ' perform simple bit shifts on the 64-bit MMX registers: the
       destination (first) operand is shifted left or right by the number
       of bits given in the source (second) operand, and the vacated bits
       are filled in with zeros (for a logical shift) or copies of the
       original sign bit (for an arithmetic right shift).

       `PSxxW' and `PSxxD' perform packed bit shifts: the destination
       operand is treated as a vector of four words or two doublewords, and
       each element is shifted individually, so bits shifted out of one
       element do not interfere with empty bits coming into the next.

       `PSLLx' and `PSRLx' perform logical shifts: the vacated bits at one
       end of the shifted number are filled with zeros. `PSRAx' performs an
       arithmetic right shift: the vacated bits at the top of the shifted
       number are filled with copies of the original top (sign) bit.

 A.131 `PSUBxx': MMX Packed Subtraction

       PSUBB mmxreg,r/m64            ; 0F F8 /r             [PENT,MMX] 
       PSUBW mmxreg,r/m64            ; 0F F9 /r             [PENT,MMX] 
       PSUBD mmxreg,r/m64            ; 0F FA /r             [PENT,MMX]

       PSUBSB mmxreg,r/m64           ; 0F E8 /r             [PENT,MMX] 
       PSUBSW mmxreg,r/m64           ; 0F E9 /r             [PENT,MMX]

       PSUBUSB mmxreg,r/m64          ; 0F D8 /r             [PENT,MMX] 
       PSUBUSW mmxreg,r/m64          ; 0F D9 /r             [PENT,MMX]

       `PSUBxx' all perform packed subtraction between their two 64-bit
       operands, storing the result in the destination (first) operand. The
       `PSUBxB' forms treat the 64-bit operands as vectors of eight bytes,
       and subtract each byte individually; `PSUBxW' treat the operands as
       vectors of four words; and `PSUBD' treats its operands as vectors of
       two doublewords.

       In all cases, the elements of the operand on the right are
       subtracted from the corresponding elements of the operand on the
       left, not the other way round.

       `PSUBSB' and `PSUBSW' perform signed saturation on the sum of each
       pair of bytes or words: if the result of a subtraction is too large
       or too small to fit into a signed byte or word result, it is clipped
       (saturated) to the largest or smallest value which _will_ fit.
       `PSUBUSB' and `PSUBUSW' similarly perform unsigned saturation,
       clipping to `0FFh' or `0FFFFh' if the result is larger than that.

 A.132 `PSUBSIW': MMX Packed Subtract with Saturation to Implied Destination

       PSUBSIW mmxreg,r/m64          ; 0F 55 /r             [CYRIX,MMX]

       `PSUBSIW', specific to the Cyrix extensions to the MMX instruction
       set, performs the same function as `PSUBSW', except that the result
       is not placed in the register specified by the first operand, but
       instead in the implied destination register, specified as for
       `PADDSIW' (section A.115).

 A.133 `PUNPCKxxx': Unpack Data

       PUNPCKHBW mmxreg,r/m64        ; 0F 68 /r             [PENT,MMX] 
       PUNPCKHWD mmxreg,r/m64        ; 0F 69 /r             [PENT,MMX] 
       PUNPCKHDQ mmxreg,r/m64        ; 0F 6A /r             [PENT,MMX]

       PUNPCKLBW mmxreg,r/m64        ; 0F 60 /r             [PENT,MMX] 
       PUNPCKLWD mmxreg,r/m64        ; 0F 61 /r             [PENT,MMX] 
       PUNPCKLDQ mmxreg,r/m64        ; 0F 62 /r             [PENT,MMX]

       `PUNPCKxx' all treat their operands as vectors, and produce a new
       vector generated by interleaving elements from the two inputs. The
       `PUNPCKHxx' instructions start by throwing away the bottom half of
       each input operand, and the `PUNPCKLxx' instructions throw away the
       top half.

       The remaining elements, totalling 64 bits, are then interleaved into
       the destination, alternating elements from the second (source)
       operand and the first (destination) operand: so the leftmost element
       in the result always comes from the second operand, and the
       rightmost from the destination.

       `PUNPCKxBW' works a byte at a time, `PUNPCKxWD' a word at a time,
       and `PUNPCKxDQ' a doubleword at a time.

       So, for example, if the first operand held `0x7A6A5A4A3A2A1A0A' and
       the second held `0x7B6B5B4B3B2B1B0B', then:

       (*) `PUNPCKHBW' would return `0x7B7A6B6A5B5A4B4A'.

       (*) `PUNPCKHWD' would return `0x7B6B7A6A5B4B5A4A'.

       (*) `PUNPCKHDQ' would return `0x7B6B5B4B7A6A5A4A'.

       (*) `PUNPCKLBW' would return `0x3B3A2B2A1B1A0B0A'.

       (*) `PUNPCKLWD' would return `0x3B2B3A2A1B0B1A0A'.

       (*) `PUNPCKLDQ' would return `0x3B2B1B0B3A2A1A0A'.

 A.134 `PUSH': Push Data on Stack

       PUSH reg16                    ; o16 50+r             [8086] 
       PUSH reg32                    ; o32 50+r             [386]

       PUSH r/m16                    ; o16 FF /6            [8086] 
       PUSH r/m32                    ; o32 FF /6            [386]

       PUSH CS                       ; 0E                   [8086] 
       PUSH DS                       ; 1E                   [8086] 
       PUSH ES                       ; 06                   [8086] 
       PUSH SS                       ; 16                   [8086] 
       PUSH FS                       ; 0F A0                [386] 
       PUSH GS                       ; 0F A8                [386]

       PUSH imm8                     ; 6A ib                [286] 
       PUSH imm16                    ; o16 68 iw            [286] 
       PUSH imm32                    ; o32 68 id            [386]

       `PUSH' decrements the stack pointer (`SP' or `ESP') by 2 or 4, and
       then stores the given value at `[SS:SP]' or `[SS:ESP]'.

       The address-size attribute of the instruction determines whether
       `SP' or `ESP' is used as the stack pointer: to deliberately override
       the default given by the `BITS' setting, you can use an `a16' or
       `a32' prefix.

       The operand-size attribute of the instruction determines whether the
       stack pointer is decremented by 2 or 4: this means that segment
       register pushes in `BITS 32' mode will push 4 bytes on the stack, of
       which the upper two are undefined. If you need to override that, you
       can use an `o16' or `o32' prefix.

       The above opcode listings give two forms for general-purpose
       register push instructions: for example, `PUSH BX' has the two forms
       `53' and `FF F3'. NASM will always generate the shorter form when
       given `PUSH BX'. NDISASM will disassemble both.

       Unlike the undocumented and barely supported `POP CS', `PUSH CS' is
       a perfectly valid and sensible instruction, supported on all
       processors.

       The instruction `PUSH SP' may be used to distinguish an 8086 from
       later processors: on an 8086, the value of `SP' stored is the value
       it has _after_ the push instruction, whereas on later processors it
       is the value _before_ the push instruction.

 A.135 `PUSHAx': Push All General-Purpose Registers

       PUSHA                         ; 60                   [186] 
       PUSHAD                        ; o32 60               [386] 
       PUSHAW                        ; o16 60               [186]

       `PUSHAW' pushes, in succession, `AX', `CX', `DX', `BX', `SP', `BP',
       `SI' and `DI' on the stack, decrementing the stack pointer by a
       total of 16.

       `PUSHAD' pushes, in succession, `EAX', `ECX', `EDX', `EBX', `ESP',
       `EBP', `ESI' and `EDI' on the stack, decrementing the stack pointer
       by a total of 32.

       In both cases, the value of `SP' or `ESP' pushed is its _original_
       value, as it had before the instruction was executed.

       `PUSHA' is an alias mnemonic for either `PUSHAW' or `PUSHAD',
       depending on the current `BITS' setting.

       Note that the registers are pushed in order of their numeric values
       in opcodes (see section A.2.1).

       See also `POPA' (section A.127).

 A.136 `PUSHFx': Push Flags Register

       PUSHF                         ; 9C                   [186] 
       PUSHFD                        ; o32 9C               [386] 
       PUSHFW                        ; o16 9C               [186]

       `PUSHFW' pops a word from the stack and stores it in the bottom 16
       bits of the flags register (or the whole flags register, on
       processors below a 386). `PUSHFD' pops a doubleword and stores it in
       the entire flags register.

       `PUSHF' is an alias mnemonic for either `PUSHFW' or `PUSHFD',
       depending on the current `BITS' setting.

       See also `POPF' (section A.128).

 A.137 `PXOR': MMX Bitwise XOR

       PXOR mmxreg,r/m64             ; 0F EF /r             [PENT,MMX]

       `PXOR' performs a bitwise XOR operation between its two operands
       (i.e. each bit of the result is 1 if and only if exactly one of the
       corresponding bits of the two inputs was 1), and stores the result
       in the destination (first) operand.