📄 init.s
字号:
AREA init, CODE, READONLY
EXPORT __main
ARM_MODE_USER EQU 0x10
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
ARM_MODE_ABORT EQU 0x17
ARM_MODE_UNDEF EQU 0x1B
ARM_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
T_BIT EQU 0x20
IRQ_STACK_SIZE EQU (3*8*4) ; 3 words per interrupt priority level
FIQ_STACK_SIZE EQU (3*4) ; 3 words
ABT_STACK_SIZE EQU (1*4) ; 1 word
UND_STACK_SIZE EQU (1*4) ; 1 word
TOP_EXCEPTION_STACK EQU 0x020F0000
TOP_APPLICATION_STACK EQU 0x020EF000
EBI_BASE EQU 0xFFE00000
EBI_CSR_0 EQU 0x01002529
EBI_CSR_1 EQU 0x02002121
EBI_CSR_2 EQU 0x20000000
EBI_CSR_3 EQU 0x30002122
EBI_CSR_4 EQU 0x02402021
EBI_CSR_5 EQU 0x02502021
EBI_CSR_6 EQU 0x06002029
EBI_CSR_7 EQU 0x70000000
EBI_RCR EQU 0x00000001
EBI_MCR EQU 0x00000006
PIO_BASE EQU 0xFFFF0000
ONCHIP_RAM EQU 0x00300000
ENTRY
__main
B InitReset ; reset
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
B irqvec ; reserved
fiqvec
B fiqvec ; reserved
VectorTable
ldr pc, [pc, #&18] ; SoftReset
ldr pc, [pc, #&18] ; UndefHandler
ldr pc, [pc, #&18] ; SWIHandler
ldr pc, [pc, #&18] ; PrefetchAbortHandler
ldr pc, [pc, #&18] ; DataAbortHandler
nop ; Reserved
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
ldr pc, [pc,#-0xF20] ; FIQ : read the AIC
;- There are only 5 offsets as the vectoring is used.
DCD SoftReset
DCD UndefHandler
DCD SWIHandler
DCD PrefetchAbortHandler
DCD DataAbortHandler
;- Vectoring Execution function run at absolut addresss
SoftReset
b SoftReset
UndefHandler
b UndefHandler
SWIHandler
b SWIHandler
PrefetchAbortHandler
b PrefetchAbortHandler
DataAbortHandler
b DataAbortHandler
InitTableEBI
DCD EBI_CSR_0
DCD EBI_CSR_1
DCD EBI_CSR_2
DCD EBI_CSR_3
DCD EBI_CSR_4
DCD EBI_CSR_5
DCD EBI_CSR_6
DCD EBI_CSR_7
DCD EBI_RCR ; REMAP command
DCD EBI_MCR ; 6 memory regions, standard read
PtEBIBase
DCD EBI_BASE ; EBI Base Address
InitReset
;- Load System EBI Base address and CSR0 Init Value
ldr r0, PtEBIBase
ldr r1, [pc,#-(8+.-InitTableEBI)]
str r1, [r0]
;-load vector table to ONCHIP_RAM
mov r8,#ONCHIP_RAM ; @ of the hard vector after remap in internal RAM 0x0
add r9, pc,#-(8+.-VectorTable) ; @ where to read values (relative)
ldmia r9!, {r0-r7} ; read 8 vectors
stmia r8!, {r0-r7}
ldmia r9!, {r0-r4} ; read 5 absolute handler addresses
stmia r8!, {r0-r4} ; store them
InitMem
sub r10, pc,#(8+.-InitTableEBI)
ldr r12, PtInitRemap
ldmia r10!, {r0-r9,r11}
stmia r11!, {r0-r9}
mov pc, r12
PtInitRemap
DCD InitStk
;------------------------------------------------------------------------------
;- Setup the stack for each mode, locate at the top of external RAM
;------------------------------------------------------------------------
InitStk
ldr r0, =TOP_EXCEPTION_STACK
;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack FIQ
sub r0, r0, #FIQ_STACK_SIZE
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ:OR:F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
;- Set up Abort Mode and set Abort Mode Stack
msr CPSR_c, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack Abort
sub r0, r0, #ABT_STACK_SIZE
;- Set up Undefined Instruction Mode and set Undef Mode Stack
msr CPSR_c, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack Undef
sub r0, r0, #UND_STACK_SIZE
;- Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
mov r13, r0 ; Init stack Sup
msr CPSR_c, #ARM_MODE_USER ; set User mode
ldr r13, =TOP_APPLICATION_STACK ; Init stack User
;------------------------------------------------------------------------------
;-Initialize the parallel I/O controller
;------------------------------------------------------------------------------
LDR R0,=PIO_BASE
LDR R1,=0xFF70FF00
STR R1,[R0,#0x04];PIO_PDR,p16-p19 and p0-p7is valueable,P23
LDR R1,=0x008F00FF
STR R1,[R0,#0x00];PIO_PER
LDR R1,=0xFFFFFFFF
STR R1,[R0,#0x20];PIO_IFER,all pins have input filter
LDR R1,=0x0
STR R1,[R0,#0x24];PIO_IFDR
LDR R1,=0xFFFFFF00
STR R1,[R0,#0x14];PIO_ODR,all pins as input EXCEPT P0-7
LDR R1,=0x000000FF
STR R1,[R0,#0x10];PIO_OER,P0-7 AS OUTPUT
;------------------------------------------------------------------------------
;-Code to initialize global variables in "C"
;------------------------------------------------------------------------------
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq NoRW
LoopRw cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc LoopRw
NoRW ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
LoopZI cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc LoopZI
IMPORT main
ldr r0, =main
mov lr, pc
bx r0
End
b End
END
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