conreg.h

uc/fs文件系统

/*
*****************************************************************************************
* name				:conreg.h															  
* note				:NetCARM7 Constant Configuration									  
* Date				:2004.1.2
* Modified by 		:Avirl																  
*****************************************************************************************
*/
#ifndef		CONREG_H
#define 	CONREG_H

#define AT91_MCK 32768000

#define 	VPint    	*(volatile unsigned int *)
#define 	VPshort  	*(volatile unsigned short *)
#define 	VPchar   	*(volatile unsigned char *)

#define		AIC_BASE	0xFFFFF000
#define 	USART0_BASE 0xFFFD0000
#define 	USART1_BASE 0xFFFCC000
#define		TIMER0BASE 	0xFFFE0000
#define		TIMER1BASE 	0xFFFE0040
#define		TIMER2BASE 	0xFFFE0080
#define 	ETH_BASE    0x20000000
/* add in 2004.5.10  */
#define		UART16C550_BASE	 0x30000000     //设置16C550的基地址，用的是NCS3片选
#define 	WATCHDOG_BASE	0xFFFF8000

#define 	PIOBASE 	0xFFFF0000


// AIC
#define 	AIC_EndOfIntCommandReg 		(VPint(AIC_BASE+0x130))
#define 	IRQStatus 					(VPint(AIC_BASE+0x108))				
#define 	IRQRawStatus 				(VPint(AIC_BASE + 0x10C))			
#define		IRQEnable 					(VPint(AIC_BASE + 0x110))			
#define 	IRQEnableSet 				(VPint(AIC_BASE + 0x120))			
#define 	IRQEnableClear 				(VPint(AIC_BASE + 0x124))       	

#define 	FIQ_SMR 		(VPint(AIC_BASE+0x000))
#define 	SWIRQ_SMR 		(VPint(AIC_BASE+0x004))

#define 	TC0IRQ_SMR 		(VPint(AIC_BASE+0x010))
#define 	TC1IRQ_SMR 		(VPint(AIC_BASE+0x014))
#define 	TC2IRQ_SMR 		(VPint(AIC_BASE+0x018))

#define 	PIOIRQ_SMR 		(VPint(AIC_BASE+0x020))

#define 	IRQ0_SMR 		(VPint(AIC_BASE+0x040))	
#define 	IRQ1_SMR 		(VPint(AIC_BASE+0x044))	
#define 	IRQ2_SMR 		(VPint(AIC_BASE+0x048))	


#define 	FIQ_SVR 		(VPint(AIC_BASE+0x080))
#define 	SWIRQ_SVR 		(VPint(AIC_BASE+0x084))
#define 	AIC_IDCR 		(VPint(AIC_BASE+0x124))
#define 	AIC_IECR 		(VPint(AIC_BASE+0x120))
	
#define 	AIC_ICCR 		(VPint(AIC_BASE+0x128))
#define 	AIC_ISCR 		(VPint(AIC_BASE+0x12c))

#define 	US0IRQ_SMR 		(VPint(AIC_BASE+0x008))
#define 	US0IRQ_SVR 		(VPint(AIC_BASE+0x088))

#define 	US1IRQ_SMR 		(VPint(AIC_BASE+0x00c))
#define 	US1IRQ_SVR 		(VPint(AIC_BASE+0x08C))

#define 	TC0IRQ_SVR 		(VPint(AIC_BASE+0x090))
#define 	TC1IRQ_SVR 		(VPint(AIC_BASE+0x094))
#define 	TC2IRQ_SVR 		(VPint(AIC_BASE+0x098))

#define 	PIOIRQ_SVR 		(VPint(AIC_BASE+0x0A0))
#define 	IRQ0_SVR 		(VPint(AIC_BASE+0x0C0))
#define 	IRQ1_SVR 		(VPint(AIC_BASE+0x0C4))
#define 	IRQ2_SVR 		(VPint(AIC_BASE+0x0C8))
#define 	AIC_IPR 		(VPint(AIC_BASE+0x10C))	

// Timer0
#define 	TC0_CCR  		(VPchar(TIMER0BASE))
#define 	TC0_CMR  		(VPint(TIMER0BASE+0x04))
#define 	TC0_IDR  		(VPchar(TIMER0BASE+0x28))
#define 	TC0_IER  		(VPchar(TIMER0BASE+0x24))
#define 	TC0_RC   		(VPint(TIMER0BASE+0x1C))
#define 	TC0_SR   		(VPint(TIMER0BASE+0x20))


// UART 0      
#define 	US0_CR       	(VPint(USART0_BASE))
#define 	US0_MR       	(VPint(USART0_BASE+0x04))
#define 	US0_IER       	(VPint(USART0_BASE+0x08))
#define 	US0_IDR       	(VPint(USART0_BASE+0x0c))
#define 	US0_IMR        	(VPint(USART0_BASE+0x10))
#define 	US0_CSR      	(VPint(USART0_BASE+0x14))
#define 	US0_RHR       	(VPchar(USART0_BASE+0x18))
#define 	US0_THR       	(VPchar(USART0_BASE+0x1C))
#define 	US0_BRGR       	(VPint(USART0_BASE+0x20))
#define 	US0_RTOR       	(VPint(USART0_BASE+0x24))
#define 	US0_TTGR       	(VPint(USART0_BASE+0x28))
#define 	US0_RPR       	(VPint(USART0_BASE+0x30))
#define 	US0_RCR       	(VPint(USART0_BASE+0x34))
#define 	US0_TPR       	(VPint(USART0_BASE+0x38))
#define 	US0_TCR       	(VPint(USART0_BASE+0x3C))

//  UART 1      
#define		US1_CR       	(VPint(USART1_BASE))
#define 	US1_MR       	(VPint(USART1_BASE+0x04))
#define 	US1_IER       	(VPint(USART1_BASE+0x08))
#define 	US1_IDR       	(VPint(USART1_BASE+0x0c))
#define 	US1_IMR        	(VPint(USART1_BASE+0x10))
#define 	US1_CSR       	(VPint(USART1_BASE+0x14))
#define 	US1_RHR       	(VPchar(USART1_BASE+0x18))
#define 	US1_THR       	(VPchar(USART1_BASE+0x1C))
#define 	US1_BRGR       	(VPint(USART1_BASE+0x20))
#define 	US1_RTOR       	(VPint(USART1_BASE+0x24))
#define 	US1_TTGR       	(VPint(USART1_BASE+0x28))
#define 	US1_RPR       	(VPint(USART1_BASE+0x30))
#define 	US1_RCR       	(VPint(USART1_BASE+0x34))
#define 	US1_TPR       	(VPint(USART1_BASE+0x38))
#define 	US1_TCR       	(VPint(USART1_BASE+0x3C))


//	PIO
#define		PIO_PER			(VPint(PIOBASE))
#define		PIO_OER			(VPint(PIOBASE+0x10))
#define		PIO_ODR			(VPint(PIOBASE+0x14))
#define		PIO_SODR		(VPint(PIOBASE+0x30))
#define		PIO_CODR		(VPint(PIOBASE+0x34))
#define		PIO_ODSR		(VPint(PIOBASE+0x38))
#define		PIO_PDSR		(VPint(PIOBASE+0x3c))


//  ETH
#define 	ETH_CR   		(VPchar(ETH_BASE))
#define 	ETH_PSTART   	(VPchar(ETH_BASE+0x1))
#define 	ETH_PSTOP   	(VPchar(ETH_BASE+0x2))
#define 	ETH_BNRY   		(VPchar(ETH_BASE+0x3))
#define 	ETH_TSR   		(VPchar(ETH_BASE+0x4))
#define 	ETH_TBCR0   	(VPchar(ETH_BASE+0x5))
#define 	ETH_TBCR1   	(VPchar(ETH_BASE+0x6))
#define 	ETH_ISR   		(VPchar(ETH_BASE+0x7))
#define 	ETH_RSAR0   	(VPchar(ETH_BASE+0x8))
#define 	ETH_RSAR1   	(VPchar(ETH_BASE+0x9))
#define 	ETH_RBCR0   	(VPchar(ETH_BASE+0x0A))
#define 	ETH_RBCR1   	(VPchar(ETH_BASE+0x0B))
#define 	ETH_RCR   		(VPchar(ETH_BASE+0x0C))
#define 	ETH_TCR   		(VPchar(ETH_BASE+0x0D))
#define 	ETH_DCR   		(VPchar(ETH_BASE+0x0E))
#define 	ETH_IMR   		(VPchar(ETH_BASE+0x0F))
#define  	ETH_Dport  		(VPchar(ETH_BASE+0x10))
#define  	ETH_Rport   	(VPchar(ETH_BASE+0x1F))
#define  	ETH_PAR0        (ETH_BASE+0x1)
#define  	ETH_MAR0        (ETH_BASE+0x8)
#define  	ETH_NCR         ETH_TBCR0

#define   	ETH_CURR  	  	ETH_ISR
#define   	ETH_CRDA0     	ETH_RSAR0
#define   	ETH_CRDA1	    ETH_RSAR1
#define   	ETH_FIFO        ETH_TBCR1

#define  	ETH_RSR         ETH_RCR
#define  	ETH_TPSR        ETH_TSR

/* add in 2004.5.10 */
//16C550
#define 	UART16C550_THR   	(VPchar(UART16C550_BASE))			//发送保持寄存器，只写
#define 	UART16C550_RBR   	(VPchar(UART16C550_BASE))			//接收缓冲寄存器，只读
#define 	UART16C550_IER    	(VPchar(UART16C550_BASE+0x1))		//中断使能寄存器
#define 	UART16C550_IIR   	(VPchar(UART16C550_BASE+0x2))       //中断识别寄存器，只读
#define 	UART16C550_FCR   	(VPint(UART16C550_BASE+0x2))		//FIFO控制寄存器，只写
#define 	UART16C550_LCR   	(VPchar(UART16C550_BASE+0x3))		//线控制寄存器
#define 	UART16C550_MCR  	(VPchar(UART16C550_BASE+0x4))		//MODEM控制寄存器
#define 	UART16C550_LSR   	(VPchar(UART16C550_BASE+0x5))		//线状态寄存器
#define 	UART16C550_MSR  	(VPchar(UART16C550_BASE+0x6))		//MODEM状态寄存器

#define 	UART16C550_DLL   	(VPchar(UART16C550_BASE))           //DLAB = 1时
#define 	UART16C550_DLM    	(VPchar(UART16C550_BASE+0x1))       //DLAB = 1时

//WATCHDOG
#define		WATCHDOG_OMR		(VPint(WATCHDOG_BASE))				//读写
#define		WATCHDOG_CMR		(VPint(WATCHDOG_BASE+0x04))			//读写
#define		WATCHDOG_CR			(VPint(WATCHDOG_BASE+0x08))			//只写
#define		WATCHDOG_SR			(VPint(WATCHDOG_BASE+0x0C))			//只读

#endif