📄 ebininew.s
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AREA BOOTROM, CODE, READONLY
ARM_MODE_SYS EQU 0x1F
ARM_MODE_IRQ EQU 0x12
I_BIT EQU 0x80
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
I_Bit EQU 0x80
F_Bit EQU 0x40
AIC_BASE EQU 0xFFFFF000
AIC_EOICR EQU 0x0130
;PIO IRQ
AIC_SMR0 EQU 0xFFFFF000
AIC_SVR0 EQU 0xFFFFF080
AIC_SMR1 EQU 0xFFFFF004
AIC_SVR1 EQU 0xFFFFF084
AIC_SMR8 EQU 0xFFFFF020
AIC_SVR8 EQU 0xFFFFF0A0
AIC_IECR EQU 0xFFFFF120
AIC_IDCR EQU 0xFFFFF124
PIO_ISR EQU 0xFFFF004C
PIO_PDSR EQU 0xFFFF003C
PIO_BASE EQU 0xFFFF0000
P0_P7MASK EQU 0xFFFFFF00
USART0 EQU 0xFFFD0000
USART1 EQU 0xFFFCC000
CS4_addr EQU 0x40000000
;LCD and keyboard
FLASHROM_addr EQU 0x01000000
AT91_MEM EQU 0xFFE00000 ; Memory controller
MEM_RCR EQU 0xFFE00020 ; remap control register
ONCHIP_RAM EQU 0x00300000 ; Onchip SRAM base address (REBOOT mode)
;ON Chip RAM
send_bufffer EQU 0x00001E00;
receive_bufffer EQU 0x00001D00;
cur_addr_download_end EQU 0x00001F84;end address of cur sector
addr_download EQU 0x00001F88;start address of download
secsize_download EQU 0x0000018C;sector size of download
debug_SP_Start EQU 0x00001F90;sector size of download
debug_SP_End EQU 0x00001F94;sector size of download
s_addr_display EQU 0x00001F98;start address of download
LCDparam EQU 0x00001F00;????????????????????
RAM_Limit EQU 0x020F0000 ;SRAM end
IRQ_Stack EQU RAM_Limit ; 1K IRQ stack at top of memory
SVC_Stack EQU RAM_Limit-2048 ; followed by SVC stack 0x1F7FF
USR_Stack EQU SVC_Stack-2048 ; followed by USR stack 0x1EFFF
FIQ_Stack EQU USR_Stack-2048 ; followed by USR stack 0x1EFFF
;XXXX 0000
;E(1),R/~W,RS(1 data,0 commmand)
LCD_CW_E EQU 0x80
;100 X
LCD_CR_E EQU 0xC0
;110 X
LCD_DW_E EQU 0xA0
;101 X
LCD_DR_E EQU 0xE0
;111 X
;write to cs4
LCD_CW EQU 0x00
;000 X
LCD_CR EQU 0x40
;010 X
LCD_DW EQU 0x20
;001 X
LCD_DR EQU 0x60
;011 X
;write to cs4
BOOTROMREG EQU 0x0100203E
;NCS0-Flash ROM
;0x0100203E
;0x0100
;%0010,0000
;%0011,1110
;0x01000000(0x-0 0000-0xF FFFF)use 0-7FFFF, 1MB (A0-A19),0 cycles added after transfer, 8 wait states 225ns ,8-bit,
CSR1DEF EQU 0x02002081
;NCS1-SRAM
;0x02000000(0x00000-3FFFF), NO TDF,4MB(A1-A21),0 cycles added after transfer, no wait states,16-bit,
;upper and lower byte with two select lines, and separate read write signals.
;2M(0x00000-0xFFFFF)
;0x00000-0x7FFFF 0x80000-0xFFFFF
;
CSR2DEF EQU 0x20000086
;disable 0x20000000,NO TDF,4MB, 8-bit, 0 wait state
CSR3DEF EQU 0x30000082
;disable 0x30000000,NO TDF,4MB, 8-bit, 0 wait state
CSR4DEF EQU 0x40002002
;LCD and keyboard
;=>8-bit 1tdf 0 waitstate
;0x4000203E
;0x4000
;%0010,0000
;%0000,0010
;0x40000000(0x0000-0xFFFF), 1MB (A0-A19),0 cycles added after transfer, 0 wait states,8-bit,
CSR5DEF EQU 0x500000BD ;disable 0x50000000,NO TDF,4MB, 16-bit, 8 wait state
CSR6DEF EQU 0x60000000 ;disable 0x60000000,
CSR7DEF EQU 0x70000000 ;disable 0x70000000,
MCRDEF EQU 0x00000006 ;4 memory regions only, standard read
addr_SVR8 EQU 0x02020000;in RaM
CODE_SVR8 EQU 0x01010000;#########in ROM
CODE_SVR8_END EQU 0x01011000
Zero EQU 0
ReadC EQU 256
WriteI EQU 512
ENTRY
vectors
B resetvec ; reqset
B undefvec ; Udef
B SoftWareINT ; SW
B pabtvec ; P abt
B dabtvec ; D abt
B rsvdvec ; reserved
ldr pc, [pc,#-&F20] ; IRQ : read the Advanced Interrupt Controller
ldr pc, [pc,#-&F20] ; FIQ : read the Advanced Interrupt Controller
resetvec
;point at the base address
LDR r0, =AT91_MEM
;program chip select and memory control registers
LDR r1, =BOOTROMREG
STR r1, [r0, #0]
LDR r1, =CSR1DEF
STR r1, [r0, #4]
LDR r1, =CSR2DEF
STR r1, [r0, #8]
LDR r1, =CSR3DEF
STR r1, [r0, #12]
LDR r1, =CSR4DEF
STR r1, [r0, #16]
LDR r1, =CSR5DEF
STR r1, [r0, #20]
LDR r1, =CSR6DEF
STR r1, [r0, #24]
LDR r1, =CSR7DEF
STR r1, [r0, #28]
LDR r1, =MCRDEF ;Memory Control Register
STR r1, [r0, #36]
copytosram
; copy first 2048 bytes of ROM to internal SRAM
; r0 destination address
; r1 source address
; r2 end of source address
; r3 corrupted
LDR r0, =ONCHIP_RAM
MOV r1, #0
ldr r2,=0x1000;4K
; r0 destination address
; r1 source address
; r2 end of source address
; r3 Temporary register
copyloop
CMP r1,r2
BGE remap
LDR r3,[r1],#4
STR r3,[r0]
LDR r3,[r0],#4
B copyloop
remap
; SRAM and ROM have same code so remap now
LDR r0, =MEM_RCR
MOV r1, #1
STR r1, [r0]
;ldr r0,=0xe51fff20
;ldr r1,=0x18
;str r0,[r1]
;ldr r0,=0xe51fff20
;ldr r1,=0x1c
;str r0,[r1]
;ldr r0,=0xea000008
;ldr r1,=0x08
;str r0,[r1]; B 0x30
;ldr r0,=0xe59f0000
;ldr r1,=0x30
;str r0,[r1];LDR r0,0x38
;ldr r0,=0xe1a0f000
;ldr r1,=0x34
;str r0,[r1];MOV pc,r0
;ldr r0,=SoftWareINT
;ldr r1,=0x38
;str r0,[r1];ADDRESS
;reset 573 to 0x00
ldrb r0,=0x00
ldr r1,=CS4_addr
strb r0,[R1]
; --- Initialise stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MOV R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =IRQ_Stack
; Enter FIQ mode and set up the FIQ stack pointer
MOV R0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =FIQ_Stack
; Set up other stack pointers if necessary
;...
; Set up the SVC stack pointer last and return to SVC mode
MOV R0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =SVC_Stack
;CODE to SRAM,INT
CODEtoEXTsram
; copy first 2048 bytes of ROM to internal SRAM
; r0 destination address
; r1 source address
; r2 end of source address
; r3 corrupted
; LDR r0,=addr_SVR8
; ldr r1,=CODE_SVR8
; ldr r2,=CODE_SVR8_END;4K
; r0 destination address
; r1 source address
; r2 end of source address
; r3 Temporary register
CODEtoEXTsramloop
;CMP r1,r2
;BGE CODEtoEXTsram_END
;LDR r3,[r1],#4
;STR r3,[r0]
;LDR r3,[r0],#4
;B CODEtoEXTsramloop
CODEtoEXTsram_END
; --- Initialise critical IO devices
LDR R0,=PIO_BASE
;P16,P17,P18,P19 for keyboard
;P0-P7 for LCD
LDR R1,=0xFF70FF00
STR R1,[R0,#0x04];PIO_PDR,p16-p19 and p0-p7is valueable,P23
LDR R1,=0x008F00FF
STR R1,[R0,#0x00];PIO_PER
LDR R1,=0xFFFFFFFF
STR R1,[R0,#0x20];PIO_IFER,all pins have input filter
LDR R1,=0x0
STR R1,[R0,#0x24];PIO_IFDR
LDR R1,=0xFFFFFF00
STR R1,[R0,#0x14];PIO_ODR,all pins as input EXCEPT P0-7
LDR R1,=0x000000FF
STR R1,[R0,#0x10];PIO_OER,P0-7 AS OUTPUT
;may be need changes
LDR R1,=0xFFF0FFFF
STR R1,[R0,#0x44];PIO_IDR interupt,p16-p19 is valueable
LDR R1,=0x000F0000
STR R1,[R0,#0x40];PIO_IER
; --- Initialise interrupt system variables here
;Setup AIC for TC1
; LDR R0,=0x00000007;AIC_SMR5 value,prior 7
; LDR R1,=AIC_SMR5
; STR R0,[R1]
; LDR R0,=addr_AIC_SVR5;AIC_SVR5 value:Addr of scankey
; LDR R1,=AIC_SVR5
; STR R0,[R1]
;Setup AIC for key_down PIO
LDR R0,=0x00000006;AIC_SMR8 value,prior 6
LDR R1,=AIC_SMR8
STR R0,[R1]
LDR R0,= PIO_int
;AIC_SVR8 value:Addr of keydown
LDR R1,=AIC_SVR8
STR R0,[R1]
;Setup AIC for FIQ
LDR R0,=0x00000046;AIC_SMR0 value,prior 6
;1 1 Edge Triggered Positive Edge Triggered
LDR R1,=AIC_SMR0
STR R0,[R1]
LDR R0,= FIQ_int
;AIC_SVR0 value:Addr of FIQ
LDR R1,=AIC_SVR0
STR R0,[R1]
;Setup AIC for SWI
LDR R0,=0x00000006;AIC_SMR1 value,prior 6
LDR R1,=AIC_SMR0
STR R0,[R1]
LDR R0,=SoftWareINT
;AIC_SVR1 value:SWI
LDR R1,=AIC_SVR1
STR R0,[R1]
;LDR R0,=0xFFFFFEFF;AIC_IDCR:ALL DISABLE ,EXCEPT 8 ENABLE
;LDR R1,=AIC_IDCR
;STR R0,[R1]
;LDR R0,=0x00000100;AIC_IECR: 8 ENABLE
;LDR R1,=AIC_IECR
;STR R0,[R1]
LDR R0,=0xFFFFFFFC;AIC_IDCR:ALL DISABLE ,EXCEPT 0,1 ENABLE
LDR R1,=AIC_IDCR
STR R0,[R1]
LDR R0,=0x00000003;AIC_IECR: 1,0 ENABLE
LDR R1,=AIC_IECR
STR R0,[R1]
LDR R1,=0xFFFFFFFF;SET OR CLEAR VALUE OUTPUT:ALL=0
LDR R0,=PIO_BASE
STR R1,[R0,#0x34];CLEAR OUTPUT DATA REGISTER
LDR R1,=PIO_PDSR
LDR R0,[R1]
BIC R0,R0,#0xFF7FFFFF
cmp r0,#0
beq bootfromH01010000
; BL LIGHTLED
;light LED
ldrb r0,=0x55
bl R0_writeP0_P7
bl init_USART0
;FIQ may be tiger
MOV R0,#Mode_SVC:OR:F_Bit; No interrupts
MSR CPSR_c, R0
;AIC_ICCR 0x128
;0xFFFFF000
;ldr r0,=0xFFFFFFFF
;ldr r1,=0xFFFFF128
;str r0,[r1]
;triger all of INT sourse,by software
;start debug from UART0
initUART0_debug
;bl INITLCD
BL LIGHTLED
LDR R1,=send_bufffer;ADDR OF STRING
LDR R0,=0x434C4557;WELC
STR R0,[R1]
LDR R0,=0x21454D4F;OME!
STR R0,[R1,#4]
LDR R5,=0x00000008
BL sendstring
;after welcome message
;PC:any key to continue
BL getbyte
CMP R5,#0x52;"R"
BNE initUART0_debug
LDR R5,=0x00000041;"A"
BL sendbyte
UART0_debugloop
; mov r0,sp
; ldr r1,=debug_SP_Start
; str r0,[r1]
stmfd sp!,{lr,pc,r0-r2}
mov r0,sp
mrs r1,cpsr
mrs r2,spsr
stmfd sp!,{r0-r12}
;current all
;Mode_USR EQU 0x10
;Mode_FIQ EQU 0x11
;Mode_IRQ EQU 0x12
;Mode_SVC EQU 0x13
;Mode_ABT EQU 0x17
;Mode_UND EQU 0x1B
;MOV R0, #Mode_USR:OR:I_Bit:OR:F_Bit ; No interrupts
;MSR CPSR_c, R0
;mov r0,r8
;mov r1,r9
;mov r2,r10
;mov r3,r11
;mov r4,r12
;mov r5,r13
;mov r6,r14
;MOV R0,#Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
;MSR CPSR_c, R0
; stmfd sp!,{r0-r6}
MOV R0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r0,r8
mov r1,r9
mov r2,r10
mov r3,r11
mov r4,r12
mov r5,r13
mov r6,r14
mrs r7,spsr
MOV R0,#Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
stmfd sp!,{r0-r7}
MOV R0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r1,r13
mov r2,r14
mrs r3,spsr
MOV R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r4,r13
mov r5,r14
mrs r6,spsr
MOV R0, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r7,r13
mov r8,r14
mrs r9,spsr
MOV R0,#Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
stmfd sp!,{r1-r9}
mov r0,sp
ldr r1,=debug_SP_End
str r0,[r1]
;all register push into stack
;save SP in :debug_SP
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