eb40800init.s

at91arm7处理器的启动源码

;初始化后COL1…COL4锁成0
;PIO中断时处理键的扫描、去抖、处理
;100X XXXX,读写键盘，防止对LCD操作


;LCD的操作中
;XXXX 1111,还可以禁止键盘

		AREA BOOTROM, CODE, READONLY
;0x0000
AT91_MEM        EQU     0xFFE00000 ; Memory controller
MEM_RCR         EQU     0xFFE00020 ; remap control register


ONCHIP_RAM      EQU     0x00300000 ; Onchip SRAM base address (REBOOT mode)
CODE_SRAM       EQU     0X02000000;SRAM ON BORAD


Mode_USR        EQU     0x10
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13

I_Bit           EQU     0x80
F_Bit           EQU     0x40


BOOTROMREG      EQU     0x0100203E
;NCS0-Flash ROM
;0x0100203E
;0x0100
;%0010,0000
;%0011,1110
;0x01000000(0x-0 0000-0xF FFFF)use 0-7FFFF, 1MB (A0-A19),0 cycles added after transfer, 8 wait states 225ns ,8-bit,

CSR1DEF         EQU     0x02003001
;NCS1-SRAM
;0x02000000(0x00000-3FFFF), NO TDF,1MB(A0-A19),0 cycles added after transfer, no wait states,16-bit,
;upper and lower byte with two select lines, and separate read write signals.

CSR2DEF         EQU     0x20000086
;disable 0x20000000,NO TDF,4MB, 8-bit, 0 wait state

CSR3DEF         EQU     0x30000082 
;disable 0x30000000,NO TDF,4MB, 8-bit,  0 wait state

CSR4DEF         EQU     0x40002002
;LCD and keyboard 
;=>8-bit  1tdf 0 waitstate
;0x4000203E
;0x4000
;%0010,0000
;%0000,0010
;0x40000000(0x0000-0xFFFF), 1MB (A0-A19),0 cycles added after transfer,  0 wait states,8-bit,


CSR5DEF         EQU     0x500000BD ;disable 0x50000000,NO TDF,4MB, 16-bit, 8 wait state
CSR6DEF         EQU     0x60000000 ;disable 0x60000000, 
CSR7DEF         EQU     0x70000000 ;disable 0x70000000, 
MCRDEF          EQU     0x00000007 ;4 memory regions only, standard read

;%_ _ _ _,_ _ _ _
;%_ _ _ _,0 0 0 0(BA)
;%0 0 1(CSEN)0(BAT),_ _ _(TDF)_(PAGES)
;%_(PAGES)0 1(WSE)_,_ _(NWS)_ _(DBW)

USART0  EQU  0xFFFD0000


TC_1_BASE       EQU      0xFFFE0040
TC_2_BASE       EQU      0xFFFE0080

TC_BCR          EQU      0xFFFE00C0
TC_BMR          EQU      0xFFFE00C4

;Time Counter 1 IRQ
AIC_SMR5        EQU      0xFFFFF014
AIC_SVR5        EQU      0xFFFFF094

;PIO IRQ
AIC_SMR8        EQU      0xFFFFF020
AIC_SVR8        EQU      0xFFFFF0A0


AIC_IECR       EQU       0xFFFFF120 
AIC_IDCR       EQU       0xFFFFF124

AIC_BASE         EQU   0xFFFFF000
AIC_EOICR        EQU   0x130

PIO_BASE       EQU       0xFFFF0000
P0_P7MASK EQU  0xFFFFFF00

C_ADD    EQU   0x10000010
D_ADD    EQU   0x10000110  

;External SRAM
;RAM_Limit       EQU     0x0207FFFF      ;SRAM end

;RAM_Limit       EQU     0x00001FFF      ;on chip SRAM end
RAM_Limit       EQU     0x00301FFF      ;on chip SRAM end


IRQ_Stack       EQU     RAM_Limit       ; 1K IRQ stack at top of memory
;SVC_Stack       EQU     RAM_Limit-2048  ; followed by SVC stack 0x1F7FF
;USR_Stack       EQU     SVC_Stack-2048  ; followed by USR stack 0x1EFFF

SVC_Stack       EQU     RAM_Limit-200  ; followed by SVC stack 0x1F7FF
USR_Stack       EQU     SVC_Stack-200  ; followed by USR stack 0x1EFFF

num_stack       EQU     USR_Stack-200-3
                      ;10位,first cell cntain the current position 0xe7fc
command_stack   EQU     num_stack-80;0xE7aC

send_bufffer     EQU  0x0200e600;e75c
receive_bufffer  EQU  0x0200e500;


;internal SRAM

LCDx_y   EQU     0x00000F00

cur_downkey       EQU     0x00000F10;(keynumber) waitting for the key up
;Last time have key down? FLAG                       (R0)
cur_column        EQU     0x00000F14; addr of column now scaning (r3)

cur_num  EQU     0x00000F20
set_num_return    EQU     0x00000F24




;//////////////////////////////
param         EQU  0x00000F28;(_v)

preset_param  EQU  param+4

current_param EQU  param+20

param_f       EQU  param+40

;//////////////////////////////


switch_sigle_continue  EQU  0xF54;ff_sigle 00_continue

param_8515_out     EQU  switch_sigle_continue+4;0xF58
;+0 F(0-255),+1 I(0-7),+2 D(0/1)


addr_download     EQU     0x00000F88;start address of download
secsize_download  EQU     0x00000F8C;sector size of download


;external ROM

;@@@@@@@@@@@@@@@@@@@@@@@@@@

m_start  EQU  0x01002ed4;########key\scan_KEY\scan_key.s
;***************************
addr_AIC_SVR5 EQU 0x000002b8;#########
addr_AIC_SVR8 EQU 0x01003d00

		ENTRY
vectors
		B       resetvec ; reqset
		B       undefvec ; Udef
		B       swivec   ; SW
		B       pabtvec  ; P abt


resetvec
	
; --- Initialise critical IO devices
         LDR   R0,=PIO_BASE 
;P16,P17,P18,P19 for keyboard
;P0-P7 for LCD

         LDR   R1,=0xFFF0FF00
         STR   R1,[R0,#0x04];PIO_PDR,p16-p19 and p0-p7is valueable
         LDR   R1,=0x000F00FF
         STR   R1,[R0,#0x00];PIO_PER
             
         LDR   R1,=0xFFFFFFFF
         STR   R1,[R0,#0x20];PIO_IFER,all pins have input filter
         LDR   R1,=0x0
         STR   R1,[R0,#0x24];PIO_IFDR

         LDR   R1,=0xFFFFFF00
         STR   R1,[R0,#0x14];PIO_ODR,all pins as input EXCEPT P0-7
         LDR   R1,=0x000000FF
         STR   R1,[R0,#0x10];PIO_OER,P0-7 AS OUTPUT

             ldrb r0,=0x55   
             
;             bl R0_writeP0_P7   
              LDR  R1,=PIO_BASE
              LDR  R3,=P0_P7MASK

              MOV  R2,R0;backup r0
              BIC  R2,R2,R3
              STR  R2,[R1,#0x30];SET OUTPUT DATA REGISTER

              MVN  R2,R0
              BIC  R2,R2,R3
              STR  R2,[R1,#0x34];CLEAR OUTPUT DATA REGISTER 
              

  
waithere        B  waithere

     
undefvec
		B       undefvec
swivec
		B       swivec
pabtvec
		B       pabtvec
dabtvec
		B       pabtvec
rsvdvec
		B       rsvdvec
progend
		END