📄 复件initbdi_key.s
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AREA BOOTROM, CODE, READONLY
;3d00
ARM_MODE_SYS EQU 0x1F
ARM_MODE_IRQ EQU 0x12
I_BIT EQU 0x80
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
I_Bit EQU 0x80
F_Bit EQU 0x40
AIC_BASE EQU 0xFFFFF000
AIC_EOICR EQU 0x0130
;PIO IRQ
AIC_SMR0 EQU 0xFFFFF000
AIC_SVR0 EQU 0xFFFFF080
AIC_SMR1 EQU 0xFFFFF004
AIC_SVR1 EQU 0xFFFFF084
AIC_SMR8 EQU 0xFFFFF020
AIC_SVR8 EQU 0xFFFFF0A0
AIC_IECR EQU 0xFFFFF120
AIC_IDCR EQU 0xFFFFF124
PIO_ISR EQU 0xFFFF004C
PIO_PDSR EQU 0xFFFF003C
PIO_BASE EQU 0xFFFF0000
P0_P7MASK EQU 0xFFFFFF00
USART0 EQU 0xFFFD0000
USART1 EQU 0xFFFCC000
CS4_addr EQU 0x40000000
;LCD and keyboard
FLASHROM_addr EQU 0x01000000
;ON Chip RAM
send_bufffer EQU 0x00000E00;
receive_bufffer EQU 0x00000D00;
cur_addr_download_end EQU 0x00000F84;end address of cur sector
addr_download EQU 0x00000F88;start address of download
secsize_download EQU 0x00000F8C;sector size of download
debug_SP_Start EQU 0x00000F90;sector size of download
debug_SP_End EQU 0x00000F94;sector size of download
s_addr_display EQU 0x00000F98;start address of download
LCDparam EQU 0x00000F00;????????????????????
RAM_Limit EQU 0x02080000 ;SRAM end
IRQ_Stack EQU RAM_Limit ; 1K IRQ stack at top of memory
SVC_Stack EQU RAM_Limit-2048 ; followed by SVC stack 0x1F7FF
USR_Stack EQU SVC_Stack-2048 ; followed by USR stack 0x1EFFF
FIQ_Stack EQU USR_Stack-2048 ; followed by USR stack 0x1EFFF
;XXXX 0000
;E(1),R/~W,RS(1 data,0 commmand)
LCD_CW_E EQU 0x80
;100 X
LCD_CR_E EQU 0xC0
;110 X
LCD_DW_E EQU 0xA0
;101 X
LCD_DR_E EQU 0xE0
;111 X
;write to cs4
LCD_CW EQU 0x00
;000 X
LCD_CR EQU 0x40
;010 X
LCD_DW EQU 0x20
;001 X
LCD_DR EQU 0x60
;011 X
;write to cs4
Zero EQU 0
ReadC EQU 256
WriteI EQU 512
ENTRY
ldr r0,=0xe51fff20
ldr r1,=0x18
str r0,[r1]
ldr r0,=0xe51fff20
ldr r1,=0x1c
str r0,[r1]
ldr r0,=0xea000008
ldr r1,=0x08
str r0,[r1]; B 0x30
ldr r0,=0xe59fc000
ldr r1,=0x30
str r0,[r1];LDR r12,0x38
ldr r0,=0xe1a0f00c
ldr r1,=0x34
str r0,[r1];MOV pc,r12
ldr r0,=SoftWareINT
ldr r1,=0x38
str r0,[r1];ADDRESS
; --- Initialise stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MOV R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =IRQ_Stack
; Enter FIQ mode and set up the FIQ stack pointer
MOV R0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =FIQ_Stack
; Set up other stack pointers if necessary
;...
; Set up the SVC stack pointer last and return to SVC mode
MOV R0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =SVC_Stack
; --- Initialise critical IO devices
LDR R0,=PIO_BASE
;P16,P17,P18,P19 for keyboard
;P0-P7 for LCD
LDR R1,=0xFFF0FF00
STR R1,[R0,#0x04];PIO_PDR,p16-p19 and p0-p7is valueable
LDR R1,=0x000F00FF
STR R1,[R0,#0x00];PIO_PER
LDR R1,=0xFFFFFFFF
STR R1,[R0,#0x20];PIO_IFER,all pins have input filter
LDR R1,=0x0
STR R1,[R0,#0x24];PIO_IFDR
LDR R1,=0xFFFFFF00
STR R1,[R0,#0x14];PIO_ODR,all pins as input EXCEPT P0-7
LDR R1,=0x000000FF
STR R1,[R0,#0x10];PIO_OER,P0-7 AS OUTPUT
;may be need changes
LDR R1,=0xFFF0FFFF
STR R1,[R0,#0x44];PIO_IDR interupt,p16-p19 is valueable
LDR R1,=0x000F0000
STR R1,[R0,#0x40];PIO_IER
; --- Initialise interrupt system variables here
;Setup AIC for TC1
; LDR R0,=0x00000007;AIC_SMR5 value,prior 7
; LDR R1,=AIC_SMR5
; STR R0,[R1]
; LDR R0,=addr_AIC_SVR5;AIC_SVR5 value:Addr of scankey
; LDR R1,=AIC_SVR5
; STR R0,[R1]
;Setup AIC for key_down PIO
LDR R0,=0x00000006;AIC_SMR8 value,prior 6
LDR R1,=AIC_SMR8
STR R0,[R1]
LDR R0,= PIO_int
;AIC_SVR8 value:Addr of keydown
LDR R1,=AIC_SVR8
STR R0,[R1]
;Setup AIC for FIQ
LDR R0,=0x00000046;AIC_SMR0 value,prior 6
;1 1 Edge Triggered Positive Edge Triggered
LDR R1,=AIC_SMR0
STR R0,[R1]
LDR R0,= FIQ_int
;AIC_SVR0 value:Addr of FIQ
LDR R1,=AIC_SVR0
STR R0,[R1]
;Setup AIC for SWI
LDR R0,=0x00000006;AIC_SMR1 value,prior 6
LDR R1,=AIC_SMR0
STR R0,[R1]
LDR R0,=SoftWareINT
;AIC_SVR1 value:SWI
LDR R1,=AIC_SVR1
STR R0,[R1]
;LDR R0,=0xFFFFFEFF;AIC_IDCR:ALL DISABLE ,EXCEPT 8 ENABLE
;LDR R1,=AIC_IDCR
;STR R0,[R1]
;LDR R0,=0x00000100;AIC_IECR: 8 ENABLE
;LDR R1,=AIC_IECR
;STR R0,[R1]
LDR R0,=0xFFFFFFFC;AIC_IDCR:ALL DISABLE ,EXCEPT 0,1 ENABLE
LDR R1,=AIC_IDCR
STR R0,[R1]
LDR R0,=0x00000003;AIC_IECR: 1,0 ENABLE
LDR R1,=AIC_IECR
STR R0,[R1]
LDR R1,=0xFFFFFFFF;SET OR CLEAR VALUE OUTPUT:ALL=0
LDR R0,=PIO_BASE
STR R1,[R0,#0x34];CLEAR OUTPUT DATA REGISTER
LDR R2,=CS4_addr
ldrb r1,=0x00
strb r1,[r2]
BL LIGHTLED
;light LED
ldrb r0,=0x55
bl R0_writeP0_P7
bl init_USART0
;FIQ may be tiger
;AIC_ICCR 0x128
;0xFFFFF000
;ldr r0,=0xFFFFFFFF
;ldr r1,=0xFFFFF128
;str r0,[r1]
;triger all of INT sourse,by software
MOV R0,#Mode_SVC ; No interrupts
MSR CPSR_c, R0
;
;start debug from UART0
initUART0_debug
;bl INITLCD
LDR R1,=send_bufffer;ADDR OF STRING
LDR R0,=0x434C4557;WELC
STR R0,[R1]
LDR R0,=0x21454D4F;OME!
STR R0,[R1,#4]
LDR R5,=0x00000008
BL sendstring
;after welcome message
;PC:any key to continue
BL getbyte
CMP R5,#0x52;"R"
BNE initUART0_debug
LDR R5,=0x00000041;"A"
BL sendbyte
UART0_debugloop
; mov r0,sp
; ldr r1,=debug_SP_Start
; str r0,[r1]
stmfd sp!,{lr,pc,r0-r2}
mov r0,sp
mrs r1,cpsr
mrs r2,spsr
stmfd sp!,{r0-r12}
;current all
;Mode_USR EQU 0x10
;Mode_FIQ EQU 0x11
;Mode_IRQ EQU 0x12
;Mode_SVC EQU 0x13
;Mode_ABT EQU 0x17
;Mode_UND EQU 0x1B
;MOV R0, #Mode_USR:OR:I_Bit:OR:F_Bit ; No interrupts
;MSR CPSR_c, R0
;mov r0,r8
;mov r1,r9
;mov r2,r10
;mov r3,r11
;mov r4,r12
;mov r5,r13
;mov r6,r14
;MOV R0,#Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
;MSR CPSR_c, R0
; stmfd sp!,{r0-r6}
MOV R0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r0,r8
mov r1,r9
mov r2,r10
mov r3,r11
mov r4,r12
mov r5,r13
mov r6,r14
mrs r7,spsr
MOV R0,#Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
stmfd sp!,{r0-r7}
MOV R0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r1,r13
mov r2,r14
mrs r3,spsr
MOV R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r4,r13
mov r5,r14
mrs r6,spsr
MOV R0, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
mov r7,r13
mov r8,r14
mrs r9,spsr
MOV R0,#Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
stmfd sp!,{r1-r9}
mov r0,sp
ldr r1,=debug_SP_End
str r0,[r1]
;all register push into stack
;save SP in :debug_SP
BL getbyte
CMP R5,#0x46;"F" File
bleq COM_download
CMP R5,#0x44;"D" Display
bleq COM_Display
CMP R5,#0x43;"C" Change
bleq COM_Change
CMP R5,#0x45;"E" Erase Flash
bleq COM_EraseFlash
CMP R5,#0x47;"G" Target Go
bleq COM_TargetGo
;swi
; SWI 0x123
B UART0_debugloop
ldmfd sp!,{r1-r9}
ldmfd sp!,{r0-r7}
;ldmfd sp!,{r0-r6}
ldmfd sp!,{r0-r12}
ldmfd sp!,{r0,r1}
ldmfd sp!,{r0-r2}
;280-byte,0x118
;----------------------------------------------------------------------
PIO_int
;- Adjust and save LR of current mode in current stack
sub r14, r14, #4
stmfd sp!, {r14}
;- Save SPSR and r0 in current stack
mrs r14, SPSR
stmfd sp!, {r0, r14}
;- Save used registers and LR_usr in the System/User Stack
stmfd sp!, {r0-r4, r14}
;-----------------------------------------------------------------------
LDR R2,=PIO_ISR
LDR R0,[R2]
BIC R0,R0,#0xFFF0FFFF
;row in r0
;1000 =>p19 0x80
;0100 =>p18 0x40
;0010 =>p17 0x20
;0001 =>p16 0x10
bl CPL_P0P7
ldr r3,=0x00000000;clr keydown
start_scan_COL
;scan col
ldr r1,=0xFFFFFFF7;1111 0111->COL4
bl delay20ms
bl CPL_P0P7
scan_nextCOL
LDR R2,=CS4_addr
bic r4,r1,#0xFFFFFFF0
strb r4,[r2]
nop
nop
nop
nop
nop
scan_thisCOL
LDR R2,=PIO_PDSR
LDR R4,[R2]
mvn r2,r4
BIC R2,R2,#0xFFF0FFFF
cmp r0,#0
beq end_of_keydown
; cmp r2,#0
; beq end_of_keydown
cmp r2,r0
beq keydown_is_curCOL
no_keydown_thiscol
mov r1,r1,ROR #1
cmp r1,#0x7FFFFFFF
beq this_scan_no_keydown
B scan_nextCOL
keydown_is_curCOL
;r1 0xFFFFFFF0
;r0 0x000F 0000->0x0000 00F0
MOV R2,R2,LSR #12
BIC R4,R1,#0xFFFFFFF0
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