enableirq.s.bak

at91arm7处理器的启动源码

    AREA BOOTROM, CODE, READONLY
;3d00
ARM_MODE_SYS     EQU   0x1F
ARM_MODE_IRQ     EQU   0x12
I_BIT            EQU   0x80
AIC_BASE         EQU   0xFFFFF000
AIC_EOICR        EQU   0x0130


;External SRAM
RAM_Limit       EQU     0x0204FFFF      ;SRAM end
;?????????????????????????????????????????????????

;RAM_Limit       EQU     0x00001FFF      ;on chip SRAM end
;RAM_Limit       EQU     0x00301FFF      ;on chip SRAM end


IRQ_Stack       EQU     RAM_Limit       ; 1K IRQ stack at top of memory
SVC_Stack       EQU     RAM_Limit-2048  ; followed by SVC stack 0x1F7FF
USR_Stack       EQU     SVC_Stack-2048  ; followed by USR stack 0x1EFFF


;cur_downkey       EQU     0x00000F10;(keynumber) waitting for the key up
;Last time have key down? FLAG                       (R0)
cur_column        EQU     0x00000F14; addr of column now scaning 

PIO_ISR           EQU     0xFFFF004C
PIO_PDSR          EQU     0xFFFF003C

CS4_addr           EQU    0x40000000
;LCD and keyboard


addr_download     EQU     0x00000F88;start address of download
secsize_download  EQU     0x00000F8C;sector size of download

USART0  EQU  0xFFFD0000

send_bufffer  EQU  0x00000E00;
receive_bufffer  EQU  0x00000D00;



C_ADD    EQU   0x10000110
D_ADD    EQU   0x10000010    
LCDparam   EQU     0x00000F00

	ENTRY
         MOV     R0, #Mode_USR:OR:I_Bit:OR:F_Bit; No FAST interrupts
         MSR     CPSR_c, R0
         LDR     sp, =USR_Stack

;light LED

               ldrb r0,=0x50    
               bl R0_writeP0_P7
         
  
waithere        B  waithere


R0_writeP0_P7
          STMFD sp!,{r1-r3,lr}

;R0 LOW 8-BIT => PIO0-PIO7
;SET R0 BEFORE CALL

              LDR  R1,=PIO_BASE
              LDR  R3,=P0_P7MASK

              MOV  R2,R0;backup r0
              BIC  R2,R2,R3
              STR  R2,[R1,#0x30];SET OUTPUT DATA REGISTER

              MVN  R2,R0
              BIC  R2,R2,R3
              STR  R2,[R1,#0x34];CLEAR OUTPUT DATA REGISTER

          LDMFD sp!,{r1-r3,PC};Return
          	
	END