msm6250_erase.scp

对nand_flash的擦除、编程算法源码

; See the ARM reference to convince yourself that this is right.
;&REFRESH_CYCLES=CONV.signedword(CONV.FLOATTOINT(&HCLK_RATE/1000000.0))
;PRINT "   MPMCDynamicRefresh: &REFRESH_CYCLES for &HCLK_RATE clock"                                
mem.write 0x63800024 0x00000002 4

; tRP: Precharge Command period                                        
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;MPMCDynamictRP
mem.write 0x63800030 0x0000000 4

; tRAS: Active to Precharge Command period   
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 50.0 MPMCDynamictRAS  
mem.write 0x63800034 0x00000001 4

; tSREX: Self-refresh exit time
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 100.0 MPMCDynamictSREX  
mem.write 0x63800038 0x00000002 4

; tAPR: last-data-out to active command time
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 100.0 MPMCDynamictAPR  
mem.write 0x6380003C 0x00000002 4

; tDAL: Data-in to active command time (or tAPW)                                          
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;GOSUB calcClkCyclesExceedTime .0 MPMCDynamictDAL  
;ENTRY &clkcycles
;d.out &MPMCDynamictDAL %LONG CONV.signedword(&clkcycles-1)
; setting per Raghu, due to ARM's bug.  052902
;MPMCDynamictDAL
mem.write 0x63800040 0x00000006 4

; tWR: Write recovery time (or tDPL or tRWL or tRDL)
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;GOSUB calcClkCyclesExceedTime 59.0 MPMCDynamictWR  
;MPMCDynamictWR
mem.write 0x63800044 0x00000001 4

; tRC: Active to active command period
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 100.0 MPMCDynamictRC  
mem.write 0x63800048 0x00000002 4
                        
; tRFC: Auto refresh period and auto refresh to active command period (or sometimes tRC)                             
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 100.0 MPMCDynamictRFC  
mem.write 0x6380004C 0x00000002 4

; tXSR: exit self-refresh to active command time
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 100.0 MPMCDynamictXSR  
mem.write 0x63800050 0x00000002 4

; tRRD: Active bank A to active bank B latency
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 20.0 MPMCDynamictRRD  
mem.write 0x63800054 0x00000000 4

; tMRD: load mode register to active command time (or tRSA)                                 
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
;calcClkCyclesExceedTime 50.0 MPMCDynamictMRD  
mem.write 0x63800058 0x00000001 4

                                                    
;
; at this point, time constants are setup in MPMC.  
;
;
; now, get the MPMC operating and configure the SDRAM devices...
;
;                                                    
; DynamicControl: issue a nop to the MPMC
;MPMCDynamicControl
mem.write 0x63800020 0x00000183 4

wait 1

; ***** ARM TRM Step 2.                 
; DynamicControl: issue a Precharge All to the MPMC
mem.write 0x63800020 0x00000103 4
        

; ***** ARM TRM Step 3.                 
; DynamicRefresh: set up the refresh and wait for 8 refresh cycles have occurred
; The value 2 is magically chosen by ARM
;MPMCDynamicRefresh
mem.write 0x63800024 0x00000002 4

; ***** ARM TRM Step 4.                 
; a little overkill here: the value of 10.ms is enough to delay 256 cycles at the 32khz sleep clock         
; For TCXO, it only needs to be 20.us.  I doubt anyone will mind the extra 9+ milliseconds of delay
wait 10 // wait more than 8 refresh cycles (16*above_value = 32) = 256 clock cycles

; ***** ARM TRM Step 5.                 
; DynamicRefresh: set refresh interval, to be the clock rate in MHz, rounded down
; ARM subtracts a margin of about 3% -- can't argue with this. 
; See the ARM reference to convince yourself that this is right.
;&REFRESH_CYCLES=(&HCLK_RATE/1000000.)*0.97
;MPMCDynamicRefresh
mem.write 0x63800024 0x00000012 4

; ***** ARM TRM Steps 6,7.                 
;
; set the RAS and CAS latencies (two clocks each == 0x202)
; then set the DynamicConfig register
;    set 01 into bits 29:28 to specify a 12-bit row width
;    Set bit 26 to indicate 4 banks/device
;    Set 011 into bits 24:22 to specify a 9-bit col width
;    set 01 into bits 4:3 to indicate LP-SDRAM memory device type
;       the bits above equal 0x14C00008
;local &DynamicConfigBaseVal 
;&DynamicConfigBaseVal=0x14C00008
;    set bits 14, 12:7 to reflect address mapping for memory part:
;        -- see each specific section below for the value
; beware, when SDRAM parts or sizes change, these have to change!

;local &DynamicConfigRegVal
  ; 128-Mbit LP-SDRAM, 8Mx16 gets bits 12, 10, 7 set
  ;   these bits = 0x1480
;  &DynamicConfigRegVal=&DynamicConfigBaseVal|0x1480
;MPMCDynamicRasCas0  
mem.write 0x63800104 0x00000202 4

;MPMCDynamicConfig0
mem.write 0x63800100 0x14C01488 4
  
                        
; ***** ARM TRM Step 8.                 
; DynamicControl: put the MPMC into Mode setting state
mem.write 0x63800020 0x00000080 4
        

; ***** ARM TRM Step 9.  
; load the Memory Parts' mode register        
; Per the ARM TRM, this is a little confusing:
; We read from an SDRAM address:  The read action programs the device,
;    and the address read indicates the configuration.
; Per the ARM PL172 TRM, 
;    A[2:0] = burst length (8 for 16-bit wide bus, 4 for 32-bit wide)
;    A[3] = 0 (sequential burst type)
;    A[6:4] = 010 (CAS latency = 2 for our timing)
;    A[11:7] = 00000 (Operating mode= standard operation)
;  this yields a value of 0x23 for 16-bit.  Then there is a confusing 
;  lookup for (16-bit, 128Mb, 8Mx16 SDRAM) on page 6-49 (equiv to 10-bit left shift)
;  to get the value of 0x00008C00 as the address to read from.
;
;  for our 32-bit SDRAM, 8Mx32 (two 8Mx16s), the values yield 0x22 for 32-bit.
;  After lookup (euqal to shift 10 bits left), the value is 0x00008800 
;local &mode_reg_val 
;  &mode_reg_val=0x08C00   
;d.in &mode_reg_val
mem.read 0x8c00,4
        
; ***** ARM TRM Step 10.  
; load the Memory Parts' extended mode register        
; this register sets partial-array self refresh and also the temp compensated self refresh
; these values are fixed as far as we are concerned for now.
;&mode_reg_val=0x00800000
;&mode_reg_val=&mode_reg_val+&EBI1_SDRAM_BASE_ADDR 
;d.in &mode_reg_val    

                                      
; ***** ARM TRM Step 11.  
; DynamicControl: put the MPMC Control into Normal mode
mem.write 0x63800020 0x00000003 4
                                                            

; ***** ARM TRM Step 12.  
; enable buffers for the first chip select
;&DynamicConfigRegVal=&DynamicConfigRegVal|0x00080000                                        
;MPMCDynamicConfig0
mem.write 0x63800100 0x14C81488 4

; set the clocks to run continuously, enabled during all times
;MPMCDynamicControl
mem.write 0x63800020 0x00000003 4


; Now setup GPIO function selects 
;
;
; GPIO_OE_0 - Turn on GPIO13 to turn off camera flash
mem.write 0x84000150 0x00002000 4

; GPIO_FUNC_SEL_0    - no alternate function
mem.write 0x84000174 0x00000000 4

; GPIO_FUNC_SEL_1    - gpio[38:33] alternate fct.
mem.write 0x84000178 0x0000007E 4

; GPIO_FUNC_SEL_4    - gpio[67:79] alternate fct.
mem.write 0x8400017C 0x00001FFF 4


; GPIO_ALT_FUNC_SEL  - default value
mem.write 0x84000180 0x00000000 4

wait 200

;Flash configure

Flash.DownLoad         on
Flash.userOption       on
F.userfilepath         MSM6250_Erase.axf

F.Erase                chip
;F.Erase                sector
;F.SectorInfo           reset
;F.sectorRange          0x000000 - 0x7F7FFF

F.FlashBase            0x000000
F.FlashSize            0x02000000
;F.RamBase              0x00800000
F.RamBase              0x01F00000
F.RamSize              0x00100000                     

;loadbin ./msm6100.bin 0x0
;load msm6100.axf
;load startac.elf

Flash.DownLoad         off

;target.disconnect

;target.connect

;reg.write pc=0xffff0000