msm6250_erase.scp

对nand_flash的擦除、编程算法源码

;============================================================================
;  Name:
;    MSM6250.SCP
;
;  Description:
;    Script file for AIJI system OpeniceA900
;
;  Execution:
;    Modify the command line load file.elf(axf) to load the file that you want.
;    For more details, refer to SCP.txt file that accompanies this.
;
; Copyright (c) 2003,2004 by AIJI system, Incorporated.  All Rights Reserved.
;----------------------------------------------------------------------------
;============================================================================
;
;                        EDIT HISTORY FOR MODULE
;
;
; when          who      what, where, why
; -------       ---      ----------------------------------------------------
; 08/27/2003   AIJI     initial release
;============================================================================;
Target.disconnect

;remote environmemt
comm.channel usb

;Debugger environmemt
SYS.JtagClock              10
SYS.SysReset               on
SYS.SmuInit                off
SYS.Endian                 Little  ;little,Big
SYS.trst                   on ; off 
SYS.rtck                   on ; off 
;SYS.reginit                   on ; off 
SYS.timeinterval              500 ; 500 millisecond 

;============================================================================;
;Processor
P.Auto
//P.Manual ARM926EJ
P.INDEX 1
P.MCUNAME  MSM6250 ;dev filename

;============================================================================;
Target.connect
// register set

; Workaround to enable searcher RAM
; Configure GPLL to output TCXO frequency
;GPLL_CTL
mem.write 0x8400130C  0x01 4

; Enable chipx8 clock regimes
;MSM_CLK_ENA0
mem.write 0x84001400 0x01000 4

Target.disconnect
Target.connect

;--------------------------------------------------------------------------
; ARM clock controller registers
;--------------------------------------------------------------------------
; MICROPROCESSOR CLOCK CONFIGURATION
; After RESET, uP clock should default to TCXO/1. 
; Clocks are not initialized here since the default values should work
; properly. MSM6250 defaults to all clocks off, so turn them on. 
; all clock regimes except ETM is turned on.
;MSM_CLK_ENA0
mem.write 0x84001400 0xFAD7DB96 4

;MSM_CLK_ENA1
write 0x84001404 0x00000007 4

; Now setup GPIO function selects 
;
;
; GPIO_FUNC_SEL_0    - no alternate function
;GPIO_FUNC_SEL0
mem.write 0x84000174 0x00000000 4

; GPIO_FUNC_SEL_1    - gpio[38:33] alternate fct.
mem.write 0x84000178 0x0000007E 4

; GPIO_FUNC_SEL_4    - gpio[67:79] alternate fct.
mem.write 0x8400017C 0x00001FFF 4

; GPIO_ALT_FUNC_SEL  - default value
mem.write 0x84000180 0x00000000 4

; Now setup EBI2 -- the same for all configurations.
;
;
;  
; BEWARE that this script has different behavior based on the value in &HCLK_RATE
; -- timing values are calculated on the fly, based off HCLK_RATE


; setup EBI2_CFG, set for NAND flash enable and ARM priority
mem.write 0x600000E0 0x02 4

;GPn_CFG0, RAM2_CFG0, ROM2_CFG0, configures timing
;GP0_CFG0
mem.write 0x600000E4 0x03111122 4
;GP1_CFG0
mem.write 0x600000EC 0x03111122 4
;RAM2_CFG0
mem.write 0x600000F4 0x03111122 4
;ROM2_CFG0
mem.write 0x600000FC 0x03111122 4

;EBI1_CSn_CFG1, configures bus sizing and write protect 
;GP0_CFG1
mem.write 0x600000E8 0x00 1 ;ram is 16 bit device and user can write memory
;GP1_CFG1
mem.write 0x600000F0 0x00 1 
;RAM2_CFG1
mem.write 0x600000F8 0x00 1 
;ROM2_CFG1
mem.write 0x60000100 0x00 1 

; LCD setup
;LCD_CFG0
mem.write 0x60000104 0x77770807 4
;LCD_CFG1
mem.write 0x60000108 0x00 4

; MSM_BRIDGE_CFG
; Not configured.  Use default value.
mem.write 0x60000080 0x00 4

; AUXMSM_BRIDGE_CFG 
; AUXMSM bridge access parameters control the hold cycles, setup cycles, and
; wait cycles for the AUXMSM-uP interface.  The register is uninitialized after
; power-up.  It is initialized to 0x0 here, to be the same as the default value
; for MSM_ACCESS_CFG.
mem.write 0x60000084 0x00 4

; Setup GPIO2 bridge to uP (setup, hold times)
;GPIO2_ACCESS_CFG
mem.write 0x60000088 0x00 4
 
;MDSP_INTF_CFG, default state
mem.write 0x6000008C 0x07 1

; ADSP_INTF_CFG
; ADSP_INTF_CFG is a write-only register, and the power up value cannot be 
; verified easily.  To be safe, set the register to default values.
mem.write 0x60000090 0x07 1


;
; now, for EBI1, setup either the MPMC or the XMEMC memories
;
;  
; BEWARE that this script has different behavior based on the value in &HCLK_RATE
; -- timing values are calculated on the fly, based off &HCLK_RATE

;EBI1_MPMC_STDY_SEL, configures static or dynamic memory on RAMCS2 and RAMCS3
; beforehand, enable chip select two to be SDRAM
mem.write 0x600000A8 0x1 4

; setup EBI1_CFG for clock invert on SDRAM clk (bit 9), Power mgmt functions, and 
; hclk debug enable
; this register will have to be reset when clock runs faster than TCXO
mem.write 0x600000A0 0x280 4

                                                                    
; ***** ARM TRM Step 1.
wait 100

; this next step just to protect the rest of the system from behavior during configuration
; Control: Enable MPMC, no mirroring, not low power mode, drain write buffers = 8
;MPMCControl
mem.write 0x63800000 0x00000009 4

wait 10 // wait until write buffers are drained -- should check status instead of wait

; control: set normal memory map, after drain buffers done, enable MPMC.
mem.write 0x63800000 0x00000001 4

; Config: 1:1 HCLK-MPMCCLK ratio, little endian formats = 0     
;MPMCConfig                              
mem.write 0x63800008 0x0000000 4

; Clear the Static memory config for the MPMC
;MPMCStaticConfig0
mem.write 0x63800200 0x81 4

; Clear the Static memory config for the MPMC
;MPMCStaticConfig1
mem.write 0x63800220 0x81 4

; Clear the Static memory config for the MPMC
;MPMCStaticConfig2
mem.write 0x63800240 0x81 4

; Clear the Static memory config for the MPMC
;MPMCStaticConfig3
mem.write 0x63800260 0x81 4


;
;
;
; Switch the Memory controller if it is not set to MPMC
;
;
;Print "   SetupMPMC: memory controller was XMEMC--setting to MPMC"
;EBI1_MEM_CTLR_SEL_CMD
mem.write 0x600000D0 0x0 4
wait 1
  
                                                                      
; DynamicControl: set clocks always clocking and enabled
;MPMCDynamicControl
mem.write 0x63800020 0x00000003 4

;;
;; Set up all the time contants for SDRAM  
;; in the MPMC.  BEWARE THAT ALL TIME CONSTANTS 
;; ARE SCALED BY THE CLOCK PERIOD SHOWN BELOW
;;
;;  Caveat: Many of these values are limited to 4 or 5-bits.  Lauterbach gives no
;;          functions to limit width.  It is exceptionally unlikely that
;;          these values will ever exceed the field width (only for super-fast
;;          microprocessors and exceptionally slow SDRAMs), but beware.
;; 

; DynamicRefresh: set refresh interval, to be the clock rate in MHz, rounded down