msm6100_code.scp

对nand_flash的擦除、编程算法源码

;============================================================================
;  Name:
;    MSM6100.SCP
;
;  Description:
;    Script file for AIJI system OpeniceA900
;
;  Execution:
;    Modify the command line load file.elf(axf) to load the file that you want.
;    For more details, refer to SCP.txt file that accompanies this.
;
; Copyright (c) 2003,2004 by AIJI system, Incorporated.  All Rights Reserved.
;----------------------------------------------------------------------------
;============================================================================
;
;                        EDIT HISTORY FOR MODULE
;
;
; when          who      what, where, why
; -------       ---      ----------------------------------------------------
; 08/27/2003   AIJI     initial release
;============================================================================;
Target.disconnect

;remote environmemt
comm.channel usb

;Debugger environmemt
SYS.JtagClock              5
SYS.SysReset               on
SYS.SmuInit                off
SYS.Endian                 Little  ;little,Big
SYS.trst                   on ; off 
SYS.rtck                   on ; off 
;SYS.reginit                   on ; off 
SYS.timeinterval              500 ; 500 millisecond 

;============================================================================;
;Processor
P.Auto
//P.Manual ARM926EJ
P.INDEX 1
P.MCUNAME  MSM6100 ;dev filename

;============================================================================;
Target.connect

// register set
// MSM_CLK_HALT
mem.write  0x80001600  0x0  4


/////////// setup MPMC ///////////////////
; Set GPIOs to support SDRAM
; GPIO32 to A1(0)/A1(24)
// GPIO_PAGE
mem.write  0x80001220  0x20  1
// GPIO_CFG
mem.write  0x80001224  0x4    1

; GPIO31 to A1(0)/A1(23)
// GPIO_PAGE
mem.write  0x80001220  0x1F  1
// GPIO_CFG
mem.write  0x80001224  0x4    1

; Setup GPIO77 to enable SDRAM_CS
// GPIO_PAGE
mem.write  0x80001220  0x4d  1
// GPIO_CFG
mem.write  0x80001224  0x4    1


;EBI1_MPMC_STDY_SEL, configures static or dynamic memory on RAMCS2 and RAMCS3
; beforehand, enable chip select two to be SDRAM
mem.write 0x600000A8 0x1 4

; setup EBI1_CFG for clock invert on SDRAM clk (bit 9), Power mgmt functions, and 
; hclk debug enable
; this register will have to be reset when clock runs faster than TCXO
mem.write 0x600000A0 0x280 4

; ***** ARM TRM Step 1.

wait 100

; this next step just to protect the rest of the system from behavior during configuration
; Control: Enable MPMC, no mirroring, not low power mode, drain write buffers = 8
mem.write 0x63800000 0x00000009  4 

wait 10

; control: set normal memory map, after drain buffers done, enable MPMC.
mem.write 0x63800000 0x00000001  4  

; Config: 1:1 HCLK-MPMCCLK ratio, little endian formats = 0                                   
// MPMCConfig 
mem.write 0x63800008 0x00000000  4 

; Clear the Static memory config for the MPMC
// MPMCStaticConfig0 
mem.write 0x63800200 0x81  4 

; Clear the Static memory config for the MPMC
// MPMCStaticConfig1 
mem.write 0x63800220 0x81  4 

; Clear the Static memory config for the MPMC
// MPMCStaticConfig2
mem.write 0x63800240 0x81  4 

; Clear the Static memory config for the MPMC
// MPMCStaticConfig3
mem.write 0x63800260 0x81  4 

; SetupMPMC: memory controller was XMEMC--setting to MPMC
// EBI1_MEM_CTLR_SEL_CMD
mem.write 0x600000D0 0x0  1 

wait 10

; DynamicControl: set clocks always clocking and enabled
// MPMCDynamicControl
mem.write 0x63800020 0x3  4 

; DynamicRefresh: set refresh interval, to be the clock rate in MHz, rounded down
; See the ARM reference to convince yourself that this is right.
// MPMCDynamicRefresh
mem.write 0x63800024 0x2  4 

; tRP: Precharge Command period                                        
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 1
// MPMCDynamictRP
mem.write 0x63800030 0x0  4 

; tRAS: Active to Precharge Command period   
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 2
// MPMCDynamictRAS
mem.write 0x63800034 0x1  4 

; tSREX: Self-refresh exit time
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 3
// MPMCDynamictSREX
mem.write 0x63800038 0x2  4 

; tAPR: last-data-out to active command time
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 3
// MPMCDynamictAPR
mem.write 0x6380003C 0x2  4 

; tDAL: Data-in to active command time (or tAPW)                                          
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 7
// MPMCDynamictDAL
mem.write 0x63800040 0x6  4 

; tWR: Write recovery time (or tDPL or tRWL or tRDL)
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 2
// MPMCDynamictWR
mem.write 0x63800044 0x1  4 

; tRC: Active to active command period
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 3
// MPMCDynamictRC
mem.write 0x63800048 0x2  4 

; tRFC: Auto refresh period and auto refresh to active command period (or sometimes tRC)                             
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 3
// MPMCDynamictRFC
mem.write 0x6380004C 0x2  4 

; tXSR: exit self-refresh to active command time
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 3
// MPMCDynamictXSR
mem.write 0x63800050 0x2  4 

; tRRD: Active bank A to active bank B latency
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 1
// MPMCDynamictRRD
mem.write 0x63800054 0x0  4 

; tMRD: load mode register to active command time (or tRSA)                                 
;  is n+1 HCLK cycles.  Enter value in nanosecs from data sheet here 
; clkcycles 2
// MPMCDynamictMRD
mem.write 0x63800058 0x1  4 

; DynamicControl: issue a nop to the MPMC
// MPMCDynamicControl
mem.write 0x63800020 0x183  4 

wait 1

; ***** ARM TRM Step 2.                 
; DynamicControl: issue a Precharge All to the MPMC
mem.write 0x63800020 0x103  4 
        

; ***** ARM TRM Step 3.                 
; DynamicRefresh: set up the refresh and wait for 8 refresh cycles have occurred
; The value 2 is magically chosen by ARM
mem.write 0x63800024 0x2  4 

; ***** ARM TRM Step 4.                 
; a little overkill here: the value of 10.ms is enough to delay 256 cycles at the 32khz sleep clock         
; For TCXO, it only needs to be 20.us.  I doubt anyone will mind the extra 9+ milliseconds of delay
wait 10

; ***** ARM TRM Step 5.                 
; DynamicRefresh: set refresh interval, to be the clock rate in MHz, rounded down
; ARM subtracts a margin of about 3% -- can't argue with this. 
; See the ARM reference to convince yourself that this is right.
; HCLK_RATE=19.2 Mhz
; REFRESH_CYCLES=(HCLK_RATE/1000000.)*0.97
mem.write 0x63800024 0x12  4 

; ***** ARM TRM Steps 6,7.                 
;
; set the RAS and CAS latencies (two clocks each == 0x202)
; then set the DynamicConfig register
;    set 01 into bits 29:28 to specify a 12-bit row width
;    Set bit 26 to indicate 4 banks/device
;    Set 011 into bits 24:22 to specify a 9-bit col width
;    set 01 into bits 4:3 to indicate LP-SDRAM memory device type
;       the bits above equal 0x14C00008
;    set bits 14, 12:7 to reflect address mapping for memory part:
;        -- see each specific section below for the value
; beware, when SDRAM parts or sizes change, these have to change!
; 128-Mbit LP-SDRAM, 8Mx16 gets bits 12, 10, 7 set
;   these bits = 0x1480
// MPMCDynamicRasCas0
mem.write 0x63800104 0x00000202  4 
// MPMCDynamicConfig0
mem.write 0x63800100 0x14C01488  4 

; ***** ARM TRM Step 8.                 
; DynamicControl: put the MPMC into Mode setting state
mem.write 0x63800020 0x00000080  4 

; ***** ARM TRM Step 9.  
; load the Memory Parts' mode register        
; Per the ARM TRM, this is a little confusing:
; We read from an SDRAM address:  The read action programs the device,
;    and the address read indicates the configuration.
; Per the ARM PL172 TRM, 
;    A[2:0] = burst length (8 for 16-bit wide bus, 4 for 32-bit wide)
;    A[3] = 0 (sequential burst type)
;    A[6:4] = 010 (CAS latency = 2 for our timing)
;    A[11:7] = 00000 (Operating mode= standard operation)
;  this yields a value of 0x23 for 16-bit.  Then there is a confusing 
;  lookup for (16-bit, 128Mb, 8Mx16 SDRAM) on page 6-49 (equiv to 10-bit left shift)
;  to get the value of 0x00008C00 as the address to read from.
;
;  for our 32-bit SDRAM, 8Mx32 (two 8Mx16s), the values yield 0x22 for 32-bit.
;  After lookup (euqal to shift 10 bits left), the value is 0x00008800 

; write at this address offset from bottom of the device.
;&mode_reg_val=&mode_reg_val+&EBI1_SDRAM_BASE_ADDR     // 0x0
;d.in &mode_reg_val
mem.read 0x8c00, 1

; ***** ARM TRM Step 10.  
; load the Memory Parts' extended mode register        
; this register sets partial-array self refresh and also the temp compensated self refresh
; these values are fixed as far as we are concerned for now.
;&mode_reg_val=0x00800000
;&mode_reg_val=&mode_reg_val+&EBI1_SDRAM_BASE_ADDR 
;d.in &mode_reg_val    
;mem.read 0x800000, 1

; ***** ARM TRM Step 11.  
; DynamicControl: put the MPMC Control into Normal mode
// MPMCDynamicControl
mem.write 0x63800020 0x00000003  4 
 
; ***** ARM TRM Step 12.  
; enable buffers for the first chip select
// MPMCDynamicConfig0
mem.write 0x63800100 0x14C81488  4 

; set the clocks to run continuously, enabled during all times
// MPMCDynamicControl
mem.write 0x63800020 0x00000003  4 

//**           This script sets up MSM6100/MSM6300's EBI2                   **
; setup EBI2_CFG, set for NAND flash enable and ARM priority
mem.write 0x600000E0 0x02  4 

;GPn_CFG0, RAM2_CFG0, ROM2_CFG0, configures timing
// GP0_CFG0
mem.write 0x600000E4 0x03111122  4 
// GP1_CFG0
mem.write 0x600000EC 0x03111122  4 
// RAM2_CFG0
mem.write 0x600000F4 0x03111122  4 
// ROM2_CFG0
mem.write 0x600000FC 0x03111122  4 

;EBI1_CSn_CFG1, configures bus sizing and write protect 
// GP0_CFG1  ;ram is 16 bit device and user can write memory
mem.write 0x600000E4 0x00  1 
// GP1_CFG1
mem.write 0x600000EC 0x0  1 
// RAM2_CFG1
mem.write 0x600000F4 0x00  1 
// ROM2_CFG1
mem.write 0x600000FC 0x00  1 

; LCD setup
// LCD_CFG0
mem.write 0x60000104 0x77770807  4 
// LCD_CFG1
mem.write 0x60000108 0x00  4 

; Setup GPIO2 bridge to uP (setup, hold times)
// GPIO2_ACCESS_CFG
mem.write 0x60000088 0x00  4 
 
;
;
; Setup the GPIOs so that are needed for EBI2
; 
; Set GPIO35 to support happy LEDs (GP_CS0) 
// GPIO_PAGE
mem.write 0x80001220 0x23  1 
// GPIO_CFG
mem.write 0x80001224 0x4  1 

; Setup GPIO78 to enable A2(20), the 20th bit of EBI2 address
// GPIO_PAGE 
mem.write 0x80001220 0x4E  1 
// GPIO_CFG
mem.write 0x80001224 0x4  1 

; Set GPIO36 to support mainboard NOR flash device (rom2_cs_n) 
// GPIO_PAGE
mem.write 0x80001220 0x24  1 
// GPIO_CFG
mem.write 0x80001224 0x4  1 

                         
; Set GPIO67 to support SRAM on RAM2_CS on EBI2
// GPIO_PAGE
mem.write 0x80001220 0x43  1 
// GPIO_CFG
mem.write 0x80001224 0x4  1 


;--------------------------------------------------------------------------
; NAND Setup 
;--------------------------------------------------------------------------

; Setup GPIO 33 so that NAND_ROM2_CS is setup (NAND flash).
// GPIO_PAGE
mem.write 0x80001220 0x21  1 
// GPIO_CFG
mem.write 0x80001224 0x4  1 

;Hard reset the NAND Controller
// NAND_FLASH_CMD
mem.write 0x64000300 0x00  4 

wait 100

;reset NAND flash controller memory 
// NAND_FLASH_CMD
mem.write 0x64000300 0x07  4 

wait 100

; enable the NAND bus (EBI2_CFG register)
// EBI2_CFG
mem.write 0x600000e0 0x2  1 

wait 2000

;Flash configure

Flash.DownLoad         on
Flash.userOption       on
F.userfilepath         MSM6100.axf

F.Erase                sector
F.SectorInfo           reset
F.sectorRange          0x000000 - 0xFFFFFF

F.FlashBase            0x000000
F.FlashSize            0x02000000
F.RamBase              0x01F00000
F.RamSize              0x00100000                     

;loadbin ./msm6100.bin 0x0
;load sntq.elf
loadbin sntq.elf 0x0  ; 捞何盒阑 荐沥秦具 钦聪促. File path & name

Flash.DownLoad         off

target.disconnect

target.connect

reg.write pc=0xffff0000

b 0x0000000

go

wait stop

unbreak 0x0